Silicon chip shallow plow groove isolation etching method

Abstract

The invention discloses a silicon chip shallow trench isolation etching method which is used for etch groove on silicon. The method comprises the following steps: A. upper layer silicon etching step; B. oxide layer etching step, which is used for etching the oxide layer between upper layer silicon and base silicon and is also used for etching partial base silicon for the top fillet etching preparation; C. base silicon etching step which is used for etching groove on silicon base and to form slippery top fillet at the junctional position of oxide layer and silicon base on the sidewall of groove. The etching process gas used in the Step B is mixed gas consisting of HBr gas and CHF3 gas. The etching process gas is ionized into active groups like Br*, CHF*, etc., and can form the top fillet during Step C. The method has the advantages of simple process with less steps, low cost and slippery top fillet formation of etching groove, and is applicable to shallow trench isolation etching and other etchings of various type of semiconductor silicon wafers.

Description

technical field [0001] The invention relates to a semiconductor silicon chip processing technology, in particular to a silicon chip shallow trench isolation etching process. Background technique [0002] At present, microelectronic technology has entered the era of VLSI and system integration, and microelectronic technology has become the symbol and foundation of the entire information age. [0003] In microelectronics technology, to manufacture an integrated circuit, it needs to go through several processes such as integrated circuit design, mask manufacturing, raw material manufacturing, chip processing, packaging, and testing. In this process, etching the semiconductor silicon wafer to form process trenches is the key technology. [0004] Semiconductor silicon wafers generally have a multi-layer structure, including a silicon upper layer and a silicon base layer. The upper silicon layer here mainly includes a SiON (hard mask) layer and a SiN layer. There is an SiO2 oxide...

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Problems solved by technology

[0013] However, the disadvantage of this technology is that the price of CH2F2 gas used in the SiO2 layer etching step is relatively high, the tail gas treatment process is more complicated, and special equipment is required, which increases the cost of customer consumption; in addition, because it includes the upper fillet etching step, There are many steps and complicated process, which reduces the production capacity of the equipment

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