Gate-oxide etching method and multi-grid-electrode manufacturing method

Abstract

The invention provides a gate-oxide etching method and a multi-grid-electrode manufacturing method. The gate-oxide etching method includes controlling over-etching time of buffered oxide etch (BOE), enabling over-etching time of the BOE to be smaller than 30% of main etching time, and matching with concentration ratio of APM. According to the method, damage on surface of a lining can be reduced on the condition that the gate-oxide is completely etched. Meanwhile, the gate-oxide etching method is applied to the multi-grid-electrode manufacturing method, and defects of particulate matters can be reduced, so that quality of multi-grid-electrode components is greatly improved.

Description

technical field [0001] The invention relates to a manufacturing process in the field of semiconductors, in particular to a method for etching a gate oxide layer in the process of manufacturing a multi-gate. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards higher component density and high integration. In the manufacturing process of some chips, the gate thickness required for these devices is often inconsistent due to the electrical properties of different devices, so a multi-gate manufacturing process has been formed in the industry. [0003] See figure 1 , taking the double gate manufacturing process as an example: define the regions of the first device 11 and the second device 12 on the substrate 10 respectively, first form a layer of gate oxide layer 13 with th...

AI Technical Summary

Problems solved by technology

The wet etching time becomes a key factor to ensure the quality of multi-gate devices: if the etching time is too short, the first gate oxide layer will not be etched clean, and the remaining gate oxide layer will be etched in the second When the gate oxide layer is fabricated, an overlap will be formed, which will cause the gate of the first device to be too high and affect the electrical properties of the device

If the etching time is too long, after the first gate oxide layer is etched, the acidic liquid in the etching solution will further corrode the surface of the silicon layer. Although the usual etching solution is not easy to react with silicon, the part of the silicon surface Molecular bonds will be destroyed, thereby forming tiny particles, which will further grow in the subsequent cleaning process, and when the gate polysilicon (poly) is made, it will cause a snowball effect in the poly layer and become large particle defects, such as figure 2 shown

Such large particles will cause bridge defects in the gate after the poly layer is etched, such as image 3 As shown, the quality of serious imaging devices

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