82results about How to "Improve solder joint reliability" patented technology

A method of manufacturing a semiconductor device includes forming printed circuit board (PCB) having an embedded interposer. A semiconductor chip or a semiconductor package is mounted onto the embedded interposer using a conductive adhesive agent. The embedded interposer has substantially the same coefficient of thermal expansion (CTE) as the semiconductor chip. The embedded interposer is formed using a semiconductor wafer.

A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

An electrical circuit arrangement comprising a circuit board and an electrical component attached thereto by a plurality of solder joints. The sizes of the joints are chosen according to a characteristic (for example the frequency) of signals to be conducted through them. The joint sizes are inversely proportional to the frequency of signals which they are arranged to conduct. The expected fatigue life of the arrangement is greater than one in which all joints are of a smaller size, as required for example for high frequency signals, and this reduces the need for component underfill.

A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

A printed circuit board and a semiconductor package module using the same in which solder joint reliability (SJR) is improved. The printed circuit board includes: a first terminal exposed to the external of the printed circuit board in a print circuit pattern to be connected to a solder ball of a semiconductor package; a second terminal exposed to the external of the printed circuit board in the printed circuit pattern to be connected to another printed circuit board; and a buffer layer, which is an insulating layer formed adjacent the first terminal, being formed of a thermal absorption material, e.g. an elastomer, configured to absorb thermal stress caused by any difference of coefficients of thermal expansion between the semiconductor package and the first terminal, wherein the printed circuit board is a multi-layered printed circuit board including alternately layered insulators and printed circuit patterns.

The under bump metallization (UBM) structure of semiconductor device comprises a substrate having a bonding pad disposed on an active surface; a UBM adhered on the bonding pad, wherein the UBM includes lateral embedded portions and the size of the UBM is larger than the size of the bonding pad; a dielectric layer over the UBM having opening that is smaller than the size of the UBM so as to allow the lateral embedded portions being embedded into the dielectric layer with a desired dimension; and a conductive ball melted on the UBM within the opening defined by the dielectric layer.

A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is disposed within the through holes A plurality of discrete contact members are located in the plurality of the through holes, within the conductive structure. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. The conductive structure can be electrically coupled to circuit geometry. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to desired circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.

The invention relates to tin-copper-based lead-free solder alloy and a preparation method thereof. The compositions in mass percentage of the alloy are 0.1 to 1.5 percent of copper, 0.001 to 1 percent of phosphor, 0 to 6 percent of bismuth, 0 to 3 percent of zinc, and the balance being tin. The preparation method comprises the following steps: 3 to 8 percent of the phosphor and 92 to 97 percent of the tin are weighed at first and placed into a graphite crucible; the mixture is covered with protective molten salt and subjected to heat preservation for 30 to 60 minutes at a temperature of between 400 and 550 DEG C; after uniform stirring, casting is performed and tin-copper intermediate alloy is obtained; the tin-copper intermediate alloy is weighed according to the fact that the phosphor occupies 0.001 to 1 percent as calculated by the total mass of 100 percent, and 0.1 to 1.5 percent of the copper, 0 to 6 percent of the bismuth, 0 to 3 percent of the zinc and residual tin are weighed and placed into the graphite crucible; the mixture is covered with the protective molten salt and subjected to heat preservation for 40 to 80 minutes at a temperature of between 450 and 550 DEG C; and after uniform stirring, the mixture is cast into ingots. The preparation method has simple preparation technique and is easy to operate; and the product of the tin-copper-based lead-free solder alloy has the advantages of good wettability, low melting point, good mechanical property, good antioxidation, low cost and so on.

High yield, high reliability, flip-chip integrated circuit (IC) packages are achieved utilizing a combination of heat and pressure to bond flip-chip die and to cure no-flow underfill material. The underfill comprises a filler or low coefficient of thermal expansion (CTE) material to decrease CTE of the cured underfill. The filler material can be selected from the group comprising silica, silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, or a mixture thereof. The filler material may also increase the viscosity of the uncured underfill and/or increase the modulus of elasticity of the cured underfill. In some method embodiments, a thermocompression bonder is used to simultaneously provide solder bump reflow and underfill curing. Application of various methods to a component package, an electronic assembly, and an electronic system are also described.

The invention provides a lead frame soldering method which is characterized in that a nickel base layer is plated on the surface of a lead frame before soldering, a tin surface layer is plated on the surface of the nickel base layer, and then follow-up operation of soldering paste coating and reflow soldering is conducted. By plating the tin surface layer as a protection layer of the nickel base layer, oxidization of the nickel base layer can be prevented, and solderability of the lead frame is improved. Black pads and brittle failure are prevented from happening, interface cavity rate is reduced, and soldering spot reliability is improved. On the basis of the existing lead frame soldering, soldering spot requirements of surface pasting components can be met by changing the plated layers of the lead frame and the content of soldering flux lead (Pb), and other procedures are not required. The whole method is simple and easy to implement and popularize.

A board structure, a ball grid array (BGA) package and method thereof and a solder ball and method thereof. The example solder ball may include a solder portion and a grooved connection portion, formed through a partitioning process, configured to fit a corresponding protruding portion on a board. The example BGA package may include a plurality of the example solder balls. The example board structure may include the example BGA package connected to the board via the grooved connection portions and the protruding portions.

The invention discloses a high-reliability application printed circuit board assembly QFN assembling and welding pretreatment method. The method comprises the following steps that 1) a carrying plateis manufactured; 2), a mesh plate is manufactured, at least one through hole corresponding to a QFN chip bonding pad is formed in the mesh plate, and the through holes form a through hole array; 3) dehumidification treatment is carried out on a QFN chip; 4), the mesh plate and the carrying plate are cleaned; 5) the mesh plate is placed on the carrying plate, and a soldering paste containing a soldering flux is printed on the carrying plate through the through hole array; 6) the QFN chip is pasted on the carrying plate with the soldering paste by a chip mounter; 7) hot air reflow soldering processing is performed on the carrying plate pasted with the QFN chip; and 8) the carrying plate pasted with the QFN chip is immersed into a cleaning agent so as to dissolve the soldering flux residue, and the QFN chip is separated from the carrying plate to complete the pre-tin coating. According to the method, the weldability of the QFN chip bonding pad is better through the pre-tin coating treatment, the welding qualification rate and reliability of the QFN chip can be improved, the stability and the service life of the printed circuit board assembly with high reliability are improved, and themaintenance cost of the system is reduced.

The invention provides a tail potting method of a cable electric coupler for a satellite. The method includes the steps that first, E-51 epoxy resin and a curing agent thereof are weighed, the E-51 epoxy resin and the curing agent are mixed according to the proportion that the E-51 epoxy resin to the curing agent is 4 to 1, and a bi-component epoxy resin pouring sealant is manufactured and is filled into a container; afterwards, a stirring defoaming machine is started, and a stirring defoaming program is set; the container filled with the bi-component epoxy resin pouring sealant is placed into the stirring defoaming machine, so that stirring and defoaming are carried out; the bi-component epoxy resin pouring sealant after stirring and defoaming is filled into an injection device, the pouring sealant is manually and slowly poured into the tail portion of the cable electric coupler, whether bubbles generate or not is observed at any time, if the bubbles generate, operation is stopped, the defoaming program is executed again, and operation continues after defoaming; at last, the potted able electric coupler is fixed to be solidified. The tail potting method of the cable electric coupler for the satellite achieves visualization of electric coupler welding spots and has the advantages of improving the reliability of the welding spots, prolonging the service life of cables and lowering the working cost.