A high speed
access bus interface for a communications network. The interface allows uni-directional transfer of data packets at a
fast path processing rate of about 10 gigabits per second. The interface uses a master port and a slave port in a
chip to
chip data transfer scheme. The master and slave ports may have one or more than one
data channel for transferring data packets. The master port includes a
clock signal for
synchronizing the transfer from the master port to the slave port. The slave may send an asynchronous
signal to the master port in order to initiate the master port to stop or stall the pipeline transfer of data packets until space is made available in the slave port buffer. In addition to the
clock synchronization, the interface utilizes an enable
signal, a start of packet signal, an
end of packet signal, an
error signal (if necessary), a last valid
byte signal, and a
parity bit signal to identify, address, each data packet in the
data stream. If a
processing error occurs, the master port
error signal to the slave port also initiates the slave port to disregard the previous data packet. The
operating frequency of 50 MHz allows the data packet transfer to exceed 10 gigabits per second.