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Efficient parallel sub-packet decoding using multiple decoders, controller and task instructions

A technology of information packet and decoder, applied in the field of decoding, can solve problems such as increasing the burden of processing capacity

Inactive Publication Date: 2011-02-23
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Supporting this higher data throughput rate taxes the processing power of various parts of the circuitry of wireless communication devices such as devices 2 and 3

Method used

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  • Efficient parallel sub-packet decoding using multiple decoders, controller and task instructions
  • Efficient parallel sub-packet decoding using multiple decoders, controller and task instructions
  • Efficient parallel sub-packet decoding using multiple decoders, controller and task instructions

Examples

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Embodiment Construction

[0024] image 3 is a simplified high-level block diagram of an exemplary wireless communication device 100. The wireless communication device 100 includes (except for components not depicted): an antenna 101 , a radio frequency (RF) integrated circuit 102 and a digital baseband integrated circuit 103 .

[0025] Figure 4 yes image 3 A more detailed block diagram of the antenna 101 and RF transceiver integrated circuit 102. The RF transceiver integrated circuit 102 includes a receive chain 104 and a transmit chain 105 . Incoming transmission 106 is received at antenna 101 and passed through duplexer 107 and matching network 108 to receive chain 104 . After being down-converted in the receive chain 104, the received signal is passed to an analog-to-digital converter (ADC) 109 in a digital baseband integrated circuit 103 for further processing. If the wireless communication device 100 is to transmit, the digital information is converted to analog form by a digital-to-analog c...

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Abstract

A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Description

[0001] Cross References to Related Applications [0002] This application claims priority under 35 U.S.C. §119 to Provisional Application No. 61 / 041,558, filed April 1, 2008, which is hereby incorporated by reference. technical field [0003] The present invention relates to decoding in communication systems. Background technique [0004] Figure 1 (Prior Art) is a diagram of one conventional type of wireless communication system for transmitting packets of information. A packet 1 of data can be transmitted from a first wireless communication device 2 to a second wireless communication device 3 . The communication device 3 includes an antenna 4 , an RF transceiver integrated circuit 5 , and a digital baseband integrated circuit 6 . The digital baseband integrated circuit 6 comprises a number of components including an analog-to-digital converter (ADC) 7 , a receive path 8 , a digital-to-analog converter (DAC) 9 , a transmit path 10 , an interrupt controller arrangement 11 a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38H03M13/29H04L1/00H04N7/26
CPCH04L1/0045H03M13/2957H03M13/6561H03M13/41H03M13/6508H04L1/0052
Inventor J·V·扎诺泰利M·M·纳特A·乔杜里K·高希R·N·沙拉W·景
Owner QUALCOMM INC
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