Asynchronous FIFO memory accomplishing unequal breadth data transmission

Abstract

The invention provides an asynchronous first-in first-out memory for realizing the width varying data transmission and a method, wherein, the memory comprises: a data cache unit, a data basic unit in the data cache unit is the common multiple of the width of the read data and the width of the written data; a writing address calculation module, which is used for calculating the specific position in the data cache that is corresponding by the current writing address according to the width of the written data; a reading address calculation module, which is used for calculating the specific position in the data cache that is corresponding by the current reading address according to the width of the read data; a reading / writing judgment module, which is used for determining the reading / writing functions according to the specific position in the data cache that is corresponding by the current writing address and the specific position in the data cache that is corresponding by the current reading address. The memory can directly calculate the specific positions of the reading / writing data with the different widths during the reading and writing logics, carry out the logical judgment, simplify the system design and improve the efficiency of data transmission.

Description

technical field [0001] The invention relates to the field of general buffer memory, in particular to an asynchronous first-in-first-out memory and method for realizing unequal width data transmission. Background technique [0002] In various applications in the computer and communication fields, data transmission between different clock domains is often required. In the case of multi-bit data transmission, in order to ensure data integrity during transmission between asynchronous clock domains, a common method is to use an asynchronous First Input First Out (FIFO) memory. The characteristic of this kind of memory is to use dual-port random access memory RAM as the storage unit, and the respective clock domains of the read / write ends are completely asynchronous, such as figure 1 as shown, figure 1 It is a schematic diagram of the working principle of the existing asynchronous FIFO memory. [0003] The write logic sends out a write enable signal, indicating that it can be w...

AI Technical Summary

Problems solved by technology

In other words, the existing asynchronous FIFO cannot directly read / write data of unequal width

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