Asynchronous FIFO memory accomplishing unequal breadth data transmission

A first-in-first-out, data transmission technology, used in data conversion, electrical digital data processing, instruments, etc., can solve the problem of inability to directly read/write data with unequal widths, and improve overall efficiency, flexible and efficient data transmission. , the effect of simplifying the system design

Inactive Publication Date: 2008-09-10
ST ERICSSON SEMICON BEIJING
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Problems solved by technology

In other words, the existing asynchronous FIFO

Method used

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  • Asynchronous FIFO memory accomplishing unequal breadth data transmission
  • Asynchronous FIFO memory accomplishing unequal breadth data transmission
  • Asynchronous FIFO memory accomplishing unequal breadth data transmission

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Embodiment Construction

[0034] The present invention improves the functions of the write logic and the read logic, so that the read / write address pointers of the asynchronous FIFO memory correspond to data cache address spaces of different widths, and the read and write addresses are converted into The corresponding address in the data cache realizes the asynchronous clock domain transmission of unequal width data.

[0035] The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings.

[0036] Such as Figure 4 as shown, Figure 4 It is a schematic diagram of the working principle of the asynchronous FIFO memory of the present invention, assuming that the write data width is x, the read data width is y, and x≠y.

[0037] Figure 4 The basic structure of the asynchronous FIFO shown with figure 2 same, but using Figure 4 The working principle diagram shown can directly realize that the width of the written da...

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Abstract

The invention provides an asynchronous first-in first-out memory for realizing the width varying data transmission and a method, wherein, the memory comprises: a data cache unit, a data basic unit in the data cache unit is the common multiple of the width of the read data and the width of the written data; a writing address calculation module, which is used for calculating the specific position in the data cache that is corresponding by the current writing address according to the width of the written data; a reading address calculation module, which is used for calculating the specific position in the data cache that is corresponding by the current reading address according to the width of the read data; a reading/writing judgment module, which is used for determining the reading/writing functions according to the specific position in the data cache that is corresponding by the current writing address and the specific position in the data cache that is corresponding by the current reading address. The memory can directly calculate the specific positions of the reading/writing data with the different widths during the reading and writing logics, carry out the logical judgment, simplify the system design and improve the efficiency of data transmission.

Description

technical field [0001] The invention relates to the field of general buffer memory, in particular to an asynchronous first-in-first-out memory and method for realizing unequal width data transmission. Background technique [0002] In various applications in the computer and communication fields, data transmission between different clock domains is often required. In the case of multi-bit data transmission, in order to ensure data integrity during transmission between asynchronous clock domains, a common method is to use an asynchronous First Input First Out (FIFO) memory. The characteristic of this kind of memory is to use dual-port random access memory RAM as the storage unit, and the respective clock domains of the read / write ends are completely asynchronous, such as figure 1 as shown, figure 1 It is a schematic diagram of the working principle of the existing asynchronous FIFO memory. [0003] The write logic sends out a write enable signal, indicating that it can be w...

Claims

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Application Information

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IPC IPC(8): G06F5/06
Inventor 周涛
Owner ST ERICSSON SEMICON BEIJING
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