FIFO protocol based digital interface circuit for SerDes technology

A digital interface and circuit technology, applied in the direction of logic circuit connection/interface layout, etc., can solve the problems of bus and SerDes bit width mismatch, feedback control signal channel transmission delay and other problems, to facilitate bit width expansion, enhance adaptability, Easy to recall effects

Inactive Publication Date: 2014-09-03
FUDAN UNIV
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Problems solved by technology

[0005] The purpose of the present invention is to provide a digital interface circuit based on the FIFO protocol in SerDes technology to effectively solve the problem of signal ...

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  • FIFO protocol based digital interface circuit for SerDes technology
  • FIFO protocol based digital interface circuit for SerDes technology
  • FIFO protocol based digital interface circuit for SerDes technology

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Embodiment Construction

[0014] At the sending end, the bus data is written into a synchronous first-in-first-out buffer queue through the FIFO protocol. The FIFO protocol means: the data w_data is registered by the write clock w_clk when the write enable w_en is active at high level. When the data is full , the w_full feedback signal is pulled high; the read data r_data is taken out by the read clock r_clk during the high-level active period of the read enable r_en, and when the data is read, the r_empty feedback signal is pulled high.

[0015] The parallel-to-serial conversion circuit of the latter stage reads the bus data from the buffer queue and divides it into several pieces of serial data and sends them to the SerDes serializer in clock cycles. Serial device, write clock, write enable, write full in advance and other low-speed control signals through the buffer (buffer) through the transmission channel.

[0016] At the receiving end, the data output by the deserializer is first written into an ...

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Abstract

The invention belongs to the field of a SerDes serial communication technology, and specifically relates to a FIFO protocol based digital interface circuit for a SerDes technology. The FIFO protocol based digital interface circuit is composed of two major parts, i.e., a sending end digital circuit and a receiving end digital circuit. According to the invention, classic synchronization and asynchronous FIFO and series-parallel and parallel-series conversion circuits in a digital system design are introduced to a SerDes digital-analog interface, the digital-analog interface is packaged to be a simple interface supporting a FIFO read-write protocol, the FIFO protocol based digital interface circuit is simple and feasible and facilitates scheduling. The ingenious use of the FIFO effectively solves the problem of signal integrity including clock zone crossing data transmission among chips, large transmission delay of a feedback control signal channel and the like. The series-parallel and parallel-series conversion circuits solve the problem of mismatch between a bus and a SerDes bid width, facilitate bit width expansion of the bus and enhance the adaptability of a circuit design scheme.

Description

technical field [0001] The invention belongs to the technical field of SerDes serial communication, and in particular relates to a digital interface circuit based on FIFO protocol in SerDes technology. Background technique [0002] With the development of electronic communication technology, the industry puts forward higher and higher requirements for the transmission rate and channel bandwidth of the data interface. The SerDes serial interface with faster speed and lower resource overhead of channel bit width has gradually become the mainstream solution. [0003] SerDes interface technology is the abbreviation of the combination of Serializer and Deserializer in English, which means that the circuit is composed of a pair of serializer and deserializer. It is a widely used time division multiplexing (Time Division Multiplex, TDM) and point-to-point (Point-to-Point, P2P) serial communication technology. SerDes technology converts multiple parallel signals into high-speed se...

Claims

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Application Information

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IPC IPC(8): H03K19/0175
Inventor 虞志益林杰周炜朱世凯周力君俞剑明
Owner FUDAN UNIV
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