An FPGA implementation method of multi-channel data source DDR buffer

Abstract

The invention discloses an FPGA implementation method of a multi-channel data source DDR buffer, including: hanging a plurality of DDR granules with the FPGA, randomly configuring the number of channels, and then arbitrating the DDR reading and writing of each channel, wnerein the arbitration rule is an arbitration rule through polling or matching the bandwidth. The invention buffers the data of each channel to the address space corresponding to each channel of the DDR, the address space size of each channel can be arbitrarily divided, the total address space size is the sum of the memory space of each DDR granule, and the channel data and the DDR are respectively transferred through asynchronous fifo. The invention flexibly and efficiently uses a plurality of DDR granules to carry out read-write arbitration on each channel, can carry out handover on the terminal domain channel when expanding a plurality of asynchronous clocks, flexibly matches the address space mapped by the cache DDR, and centralizes the cache data bandwidth of the plurality of DDRs to cache the arbitrated channel.

Description

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AI Technical Summary

Benefits of technology

This technology allows for efficient use of RAM (Random Access Memory) resources while still allowing different types of signals or devices access at once without interfering with them.

Problems solved by technology

This patented technical problem addressed in the patents relates to improving the efficiency and versatility of accessing memory from an integrated circuit (IC) chip through different types of interfaces such as serial ports or parallel port connections.

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