Virtual IO inter-chip connection circuit for FPGAs

Abstract

The present invention provides a virtual IO inter-chip connection circuit for FPGAs. The circuit comprises a clock module, a sending FPGA end circuit, a transmission module and a receiving FPGA end circuit. The sending FPGA end circuit comprises a data coding module for generating coded data; a first asynchronous FIFO which caches coded data written by the data coding module according to a coding clock and an asynchronous FIFO write protocol; and a sending module which sends data of at least two bits and a differential serial clock read from the first asynchronous FIFO until all the coded data is sent. The receiving FPGA end circuit comprises a receiving module for receiving the data of at least two bits and the differential serial clock until all the coded data is received; a second asynchronous FIFO which caches the data of at least two bits written by the receiving module according to the asynchronous FIFO write protocol and the differential serial clock until all the coded data is written; and a data decoding module which decodes the coded data synchronously. According to the invention, the transmission bandwidth and the transmission rate can be increased arbitrarily within a considerable range while the bit error rate can be reduced greatly.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to an FPGA virtual IO chip interconnection circuit. Background technique [0002] Since the launch of the world's first FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) product in 1985, FPGA has begun to occupy the mainstream of IC (Integrated Circuit, integrated circuit) design verification, relying on its unique advantages to start Gradually replace individual custom chips. At the same time, with the rapid development of the microelectronics industry, the logic resources required for IC design verification are also increasing rapidly. The logic resources of a single FPGA often cannot meet the needs of IC design verification. At this time, it is necessary to interconnect two or more FPGAs to expand resources, but because the interconnection between FPGAs occupies too many interface IOs (Input / Output, input / output), it seriously limits the development of IC...

AI Technical Summary

Problems solved by technology

However, the low bandwidth, low rate, and high bit error rate transmission caused by the low-frequency standard clock and fixed data bit width seriously limit the application environment of this technical solution, which is not very helpful for IC design verification.

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