Asynchronous AXI bus structure with built-in cross point queue

Abstract

The invention discloses an asynchronous AXI bus structure with a built-in cross point queue. The asynchronous AXI bus structure comprises an AXI bus structure and a cross point queue communication structure; the AXI bus structure comprises five channels, namely an address writing channel, a data writing channel, a writing return channel, an address reading channel and a data reading channel; the cross point queue communication structure satisfies an AXI bus protocol and is built in a communication structure for realizing inter-core communication; primary devices communicate by adopting the cross point queue communication structure; the address writing channel, the data writing channel and the writing return channel form a writing operation; and the address reading channel and the data reading channel form a reading operation. The structure can reduce resource consumption, realize parallel working of all primary devices and improve parallelism; due to the adoption of the cross point queue structure, the performance bottleneck, namely a handshake closed loop, of an on-chip communication network is broken through, and a low-delay communication function is realized; and the cross point queue is realized by adopting asynchronous FIFO, so that a mode of local synchronization and integral asynchronization is realized.

Description

technical field [0001] The invention belongs to the technical field of inter-core communication in a multi-core on-chip system, and in particular relates to an asynchronous AXI bus structure with a built-in intersection queue. Background technique [0002] 1. AXI bus protocol [0003] AXI (Advanced eXtensible Interface) is a bus protocol. This protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus for high performance, high bandwidth, and low latency. . Its address / control and data phases are separated, and it supports unaligned data transmission. At the same time, in burst transmission, only the first address is needed, while separate read and write data channels, and supports significant transmission access and out-of-order access, and Easier line timing closure. AXI is a new high-performance protocol in AMBA. AXI technology enriches the existing AMBA standard content to meet the ne...

AI Technical Summary

Problems solved by technology

[0009] Aiming at the problems of insufficient communication parallelism and large resource consumption of the master device in the traditional AXI bus stru...

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