8 results about "Asynchronous serial communication" patented technology

The utility model provides a serial communication isolation circuit relates to serial communication technical field, and this circuit includes: protocol conversion module, isolation power module, at least two isolated communication channels, protocol conversion module is used for converting computer interface signal into asynchronous serial communication protocol signal, the input of isolation power module is used for connecting input power supply, and input power supply is the power supply provided for protocol conversion module or is the external input power supply of direct connection, and isolation power module is used for converting input power supply into isolation power supply, isolation communication channel is connected with protocol conversion module, and each isolation communication channel includes: first opto -coupler isolation module and second opto -coupler isolation module, the isolation power input of first opto -coupler isolation module and second opto -coupler isolation module is connected to the output of isolation power module, and isolation power module is used for providing isolation power supply for first opto -coupler isolation module, second opto -coupler isolation module.

The invention discloses a multi-screen synchronous display control system based on a micro-control unit and asynchronous serial communication. The system comprises a micro-control unit, a communication device and at least two display screens, the micro-control unit and the communication device are connected based on asynchronous serial communication, and each display screen comprises an SPI interface and is connected to a corresponding SPI channel of the micro-control unit; the communication equipment is used for sending a data frame to the micro-control unit based on asynchronous serial communication, and the data frame at least comprises one of image data and an image control instruction; and the micro-control unit is used for receiving and analyzing the data frame and controlling each display screen based on the image control instruction so as to synchronously display the image data on each display screen. By means of the mode, the single micro-control unit can control the at least two display screens to achieve multi-screen synchronous display, and the hardware cost is reduced; through an asynchronous serial communication protocol, real-time remote control and dynamic image updating are realized, and debugging and maintenance are facilitated.

The application relates to a serial port data metastable state elimination circuit, system and method. The serial port data metastable state elimination circuit is provided with a high-frequency clock signal generation circuit. A third clock signal with a higher frequency than the frequencies of two clock signals (a first clock signal and a second clock signal) in data synchronization can be introduced. UART data conforming to a single-bit asynchronous serial communication of a UART protocol is output through a data serial port. A metastable state elimination circuit is arranged to eliminate the metastable state. The first clock signal and the second clock signal after synchronization are output to a metastable state detection circuit. After processing by the metastable state detection circuit, a flag signal indicating whether the metastable state is generated can be output. Whether the metastable state is eliminated can be judged.

The invention discloses an asynchronous serial communication method and system based on single-line time coding, relates to the technical field of asynchronous serial communication, and is cooperatively completed by a sending device and a receiving device. A sending end detects the state of a line before communication, and when the line continues to be in an idle state with the low level exceeding 500 microseconds, transmission is initiated. During sending, the data frame is converted into a pulse sequence with a specific width according to a time coding protocol, conflict detection is executed after each high-level pulse, and sending is terminated when a line is found to be pulled down. And the receiving end identifies the communication start by monitoring the start bit pulse pair, so as to calibrate the time sequence of the receiving end. When a data bit is decoded, the pulse width is accurately measured by sampling for multiple times and averaging, and a logic value is judged according to a width range. A pull-up resistor, open-drain output and an RC low-pass filter are combined on hardware to ensure signal quality, and a low-power-consumption mode is supported to enter in an idle state.

The invention relates to the technical field of data storage, and discloses a hardware optimization method for a test item, and the method comprises an upper computer which is a PC end; the SOC module is a system-on-chip, the SOC module is a control core of the whole test system, and communication of the test system is achieved; the MCU control module performs asynchronous serial communication with an upper computer through a UART (Universal Asynchronous Receiver / Transmitter) interface, performs high-speed data exchange with the master control SOC module through an SPI (Serial Peripheral Interface) interface, completes communication between the upper computer and the SOC module through the MCU control module, and controls power on and power off of the SOC module at the same time; and the DDR end of the MCU control module is connected with the DDR module, and the MCU control module is used for carrying out current test on the DDR module. According to the invention, the test coverage rate, the signal integrity and the test efficiency are improved.

The application provides a self-synchronous receiving method, device, equipment, medium and program product for UART asynchronous serial communication, the method comprising: continuously sampling a serial input signal of a UART receiving pin, and forming a window sequence updated over time according to a preset window length; performing synchronization pattern detection on the window sequence, and generating a synchronization trigger signal when the window sequence meets a preset synchronization pattern; performing synchronization hold control when the synchronization trigger signal is generated, masking a new synchronization trigger during the synchronization hold, and outputting a synchronization enable signal for bit timing based on the synchronization trigger signal; and triggering bit-level resolution of the received serial data and driving receiving state update by using the synchronization enable signal to complete the reception of a frame of data. The application provides a self-synchronous receiving mechanism without fixed baud rate configuration, high synchronization accuracy and strong robustness, and can maintain reliable communication performance in low-power embedded systems and high-noise application environments.

The application discloses a kind of array receiver multi-path DDC synchronous acquisition output system and implementation method, its system includes main channel receiver, array processing board and auxiliary channel receiver, and reception channel is equipped by radio frequency and digital processing module on main channel receiver and auxiliary channel receiver;The application adopts synchronous interface design, utilizes asynchronous serial communication protocol with synchronous pulse, realizes multi-path DDC data synchronous control and state return, is realized with few control line, and wiring is simple and low in cost, and using array receiver address coding and the design of synchronous pulse time slot, the state return and instruction control of multiple reception channels and multiple DDC data are well solved, in addition, priority arbitration mechanism is used, the multi-path DDC multiple sampling rate data transmission flow control of array receiver is solved, avoids the problem of data loss caused by buffer overflow, has data buffer state monitoring function, and improves buffer utilization.

This invention relates to the field of data storage technology and discloses a hardware optimization method for a test project. The method includes: a host computer (PC); a System-on-Chip (SOC) module, which is the control core of the entire test system and enables communication within the system; an MCU control module, which communicates asynchronously with the host computer via a UART interface and simultaneously exchanges high-speed data with the main SOC module via an SPI interface, thus facilitating communication between the host computer and the SOC module and controlling the SOC module's power supply; and a DDR module, whose DDR pin is connected to the MCU control module, allowing the MCU control module to perform current testing on the DDR module. This invention improves test coverage, signal integrity, and test efficiency.