21 results about "Asynchronous serial communication" patented technology

The utility model provides a serial communication isolation circuit relates to serial communication technical field, and this circuit includes: protocol conversion module, isolation power module, at least two isolated communication channels, protocol conversion module is used for converting computer interface signal into asynchronous serial communication protocol signal, the input of isolation power module is used for connecting input power supply, and input power supply is the power supply provided for protocol conversion module or is the external input power supply of direct connection, and isolation power module is used for converting input power supply into isolation power supply, isolation communication channel is connected with protocol conversion module, and each isolation communication channel includes: first opto -coupler isolation module and second opto -coupler isolation module, the isolation power input of first opto -coupler isolation module and second opto -coupler isolation module is connected to the output of isolation power module, and isolation power module is used for providing isolation power supply for first opto -coupler isolation module, second opto -coupler isolation module.

To make communication data flexible when communication speed in asynchronous serial communication is adjusted.SOLUTION: A communication device includes: a timing unit that measures a first time indicating the duration of a first signal level and a second time indicating the duration of a second signal level in communication data input from an opposing device; a counting unit that counts a first number indicating the number of bits of the first signal level and a second number indicating the number of bits of the second signal level; a selection unit that selects either the first time or the second time based on the first number and the second number; and an adjustment unit that adjusts communication speed in asynchronous serial communication with the opposing device based on either the first time or the second time in accordance with the selection result.SELECTED DRAWING: Figure 4

The application discloses a fly-by-wire bus control system and method based on RS485 communication, which is used for establishing a fly-by-wire communication link between at least one flight control computer and at least one control unit. The fly-by-wire bus control system comprises a plurality of communication nodes connected in communication, each of the communication nodes comprising a bus controller, an asynchronous serial communication controller and an RS485 transmission interface. One end of the bus controller is connected in bidirectional communication with one end of the asynchronous serial communication controller, the other end of the asynchronous serial communication controller is connected in bidirectional communication with the RS485 transmission interface, and the other end of the bus controller is connected in bidirectional communication with an application layer chip. The RS485 transmission interface is used for physical layer connection. The fly-by-wire bus control system based on RS485 communication is constructed through the series connection of the bus controller, the asynchronous serial communication controller and the RS485 transmission interface, and the reliability of flight control message transmission is greatly improved.

A gate driver circuit and a corresponding gate driver system is presented. The gate driver circuit may be configured to drive a gallium nitride GaN transistor. The gate driver circuit may comprise a communication interface configured to receive a gate driver parameter. The communication interface may be an asynchronous serial communication interface, such as e.g. an UART communication interface. The gate driver parameter may be forwarded from one gate driver circuit to the next using the asynchronous serial communication protocol. One or more digital isolators may be coupled between the gate driver circuits.

The invention discloses a multi-screen synchronous display control system based on a micro-control unit and asynchronous serial communication. The system comprises a micro-control unit, a communication device and at least two display screens, the micro-control unit and the communication device are connected based on asynchronous serial communication, and each display screen comprises an SPI interface and is connected to a corresponding SPI channel of the micro-control unit; the communication equipment is used for sending a data frame to the micro-control unit based on asynchronous serial communication, and the data frame at least comprises one of image data and an image control instruction; and the micro-control unit is used for receiving and analyzing the data frame and controlling each display screen based on the image control instruction so as to synchronously display the image data on each display screen. By means of the mode, the single micro-control unit can control the at least two display screens to achieve multi-screen synchronous display, and the hardware cost is reduced; through an asynchronous serial communication protocol, real-time remote control and dynamic image updating are realized, and debugging and maintenance are facilitated.

A gate driver circuit and a corresponding gate driver system is presented. The gate driver circuit may be configured to drive a gallium nitride GaN transistor. The gate driver circuit may comprise a communication interface configured to receive a gate driver parameter. The communication interface may be an asynchronous serial communication interface, such as e.g. an UART communication interface. The gate driver parameter may be forwarded from one gate driver circuit to the next using the asynchronous serial communication protocol. One or more digital isolators may be coupled between the gate driver circuits.

The application relates to a serial port data metastable state elimination circuit, system and method. The serial port data metastable state elimination circuit is provided with a high-frequency clock signal generation circuit. A third clock signal with a higher frequency than the frequencies of two clock signals (a first clock signal and a second clock signal) in data synchronization can be introduced. UART data conforming to a single-bit asynchronous serial communication of a UART protocol is output through a data serial port. A metastable state elimination circuit is arranged to eliminate the metastable state. The first clock signal and the second clock signal after synchronization are output to a metastable state detection circuit. After processing by the metastable state detection circuit, a flag signal indicating whether the metastable state is generated can be output. Whether the metastable state is eliminated can be judged.

The invention discloses an asynchronous serial communication method and system based on single-line time coding, relates to the technical field of asynchronous serial communication, and is cooperatively completed by a sending device and a receiving device. A sending end detects the state of a line before communication, and when the line continues to be in an idle state with the low level exceeding 500 microseconds, transmission is initiated. During sending, the data frame is converted into a pulse sequence with a specific width according to a time coding protocol, conflict detection is executed after each high-level pulse, and sending is terminated when a line is found to be pulled down. And the receiving end identifies the communication start by monitoring the start bit pulse pair, so as to calibrate the time sequence of the receiving end. When a data bit is decoded, the pulse width is accurately measured by sampling for multiple times and averaging, and a logic value is judged according to a width range. A pull-up resistor, open-drain output and an RC low-pass filter are combined on hardware to ensure signal quality, and a low-power-consumption mode is supported to enter in an idle state.

The invention relates to the technical field of data storage, and discloses a hardware optimization method for a test item, and the method comprises an upper computer which is a PC end; the SOC module is a system-on-chip, the SOC module is a control core of the whole test system, and communication of the test system is achieved; the MCU control module performs asynchronous serial communication with an upper computer through a UART (Universal Asynchronous Receiver / Transmitter) interface, performs high-speed data exchange with the master control SOC module through an SPI (Serial Peripheral Interface) interface, completes communication between the upper computer and the SOC module through the MCU control module, and controls power on and power off of the SOC module at the same time; and the DDR end of the MCU control module is connected with the DDR module, and the MCU control module is used for carrying out current test on the DDR module. According to the invention, the test coverage rate, the signal integrity and the test efficiency are improved.

The invention provides a self-synchronizing receiving method and device for UART asynchronous serial communication, equipment, a medium and a program product, and the method comprises the steps: carrying out the continuous sampling of a serial input signal of a UART receiving pin, and forming a window sequence which is updated along with the time according to a preset window length; performing synchronization mode detection on the window sequence, and when the window sequence meets a preset synchronization mode, generating a synchronization trigger signal; performing a synchronization hold control when the synchronization trigger signal is generated, masking a new synchronization trigger during a synchronization hold period, and outputting a synchronization enable signal for bit timing based on the synchronization trigger signal; and triggering bit-level analysis on the received serial data by utilizing the synchronous enable signal and driving the receiving state to update so as to complete the receiving of a frame of data. The invention provides a self-synchronization receiving mechanism which does not need fixed baud rate configuration, is high in synchronization precision and strong in robustness, and can maintain reliable communication performance in a low-power-consumption embedded system and a high-noise application environment.

The industrial vehicle-mounted computer comprises a code scanning gun fixing frame and a handheld code scanning gun interface module (8), and further comprises a part or all of a four-path camera interface module (9), a half-duplex asynchronous serial communication bus interface module (10), a USB interface module (11) and an NFC module (12) which are electrically connected. A lower support (7) in the code scanning gun fixing frame is fixedly connected with the side face of the shell (1), an upper support (6) is provided with a hollowed-out area, and when the handheld end of the handheld code scanning gun is inserted into the hollowed-out area, the code scanning end of the handheld code scanning gun is erected on the upper support (6). The power supply module (4), the core board module (3), the handheld code scanning gun interface module (8) and a communication interface / charging interface in the handheld code scanning gun form a working circuit / charging circuit of the handheld code scanning gun; according to the technical scheme provided by the invention, the expandability of the industrial vehicle-mounted computer is improved, so that the practicability and the application range of the industrial vehicle-mounted computer are improved.

The present invention relates to the field of serial communication technologies, and in particular to a self-learning asynchronous serial communication clock error correction algorithm. The algorithm includes the following steps: perform normal distribution sampling, select a small batch of MCUs to be used, and through means such as a logic analyzer or an oscilloscope, select the MCUs with the built-in oscillator frequency error at the central value. Set the timer value with a duration of 1 bit for the selected MCU, and the timer value will be solidified into the program as the timer reference value; The error correction algorithm proposed by the present invention can greatly improve the timing sampling accuracy, enable the built-in oscillators with large errors to be applied to serial communications with high-precision requirements, and has good effects in actual measurements in one-to-one or one-to-many serial communications. In the case of a very large MCU clock error, the sampling timings are very consistent and there is sufficient time margin, which not only reduces the cost of the MCU during use but also obtains good consistency, resulting in good economic benefits.

The application provides a self-synchronous receiving method, device, equipment, medium and program product for UART asynchronous serial communication, the method comprising: continuously sampling a serial input signal of a UART receiving pin, and forming a window sequence updated over time according to a preset window length; performing synchronization pattern detection on the window sequence, and generating a synchronization trigger signal when the window sequence meets a preset synchronization pattern; performing synchronization hold control when the synchronization trigger signal is generated, masking a new synchronization trigger during the synchronization hold, and outputting a synchronization enable signal for bit timing based on the synchronization trigger signal; and triggering bit-level resolution of the received serial data and driving receiving state update by using the synchronization enable signal to complete the reception of a frame of data. The application provides a self-synchronous receiving mechanism without fixed baud rate configuration, high synchronization accuracy and strong robustness, and can maintain reliable communication performance in low-power embedded systems and high-noise application environments.

The invention discloses an electric vertical take-off and landing telex bus control system and method based on RS485 communication. The system is used for establishing a telex communication link between at least one flight control computer and at least one control unit. The fly-by-wire bus control system comprises a plurality of communication nodes in communication connection, and each communication node comprises a bus controller, an asynchronous serial communication controller and an RS485 transmission interface. One end of the bus controller is in bidirectional communication connection with one end of the asynchronous serial communication controller, the other end of the asynchronous serial communication controller is in bidirectional communication connection with the RS485 transmission interface, and the other end of the bus controller is in bidirectional communication connection with the application layer chip; and the RS485 transmission interface is used for physical layer connection. The bus controller, the asynchronous serial controller and the RS485 transmission interface are connected in series, a telex bus control system based on RS485 communication is constructed, and the reliability of flight control message transmission is greatly improved.

The present invention relates to the field of asynchronous serial communication technology, and specifically to an asynchronous serial communication protocol automatic identification method, system, device and medium, which can calculate the baud rate of the protocol by using the time difference of pulses of different widths; use the high-frequency logic circuit of programmable logic to quickly compare the data in the cache, and the identification speed is relatively fast, which is very beneficial for on-site equipment layout and application scenarios where the protocol is unknown. The present invention can calculate the baud rate by sampling 3-6 low pulse width counts, and calculate the minimum unit value by using the different length values ​​of the 3-6 pulses themselves and the difference between them; use the time difference of pulses of different widths to calculate the baud rate of the protocol, and then cache the online data into a programmable logic device according to the baud rate, and use the high-frequency logic circuit of programmable logic to quickly compare the data in the cache, thereby obtaining the data format and finally completing the protocol identification.

The invention relates to a programmable gate driver circuit for an integrated power switch. A gate driver circuit and a corresponding gate driver system are presented. The gate driver circuit may be configured to drive a gallium nitride (GaN) transistor. The gate driver circuit may include a communication interface configured to receive gate driver parameters. The communication interface may be an asynchronous serial communication interface (such as, for example, a UART communication interface). The gate driver parameters may be forwarded from one gate driver circuit to the next using an asynchronous serial communication protocol. One or more digital isolators may be coupled between the gate driver circuits.

The application discloses a kind of array receiver multi-path DDC synchronous acquisition output system and implementation method, its system includes main channel receiver, array processing board and auxiliary channel receiver, and reception channel is equipped by radio frequency and digital processing module on main channel receiver and auxiliary channel receiver;The application adopts synchronous interface design, utilizes asynchronous serial communication protocol with synchronous pulse, realizes multi-path DDC data synchronous control and state return, is realized with few control line, and wiring is simple and low in cost, and using array receiver address coding and the design of synchronous pulse time slot, the state return and instruction control of multiple reception channels and multiple DDC data are well solved, in addition, priority arbitration mechanism is used, the multi-path DDC multiple sampling rate data transmission flow control of array receiver is solved, avoids the problem of data loss caused by buffer overflow, has data buffer state monitoring function, and improves buffer utilization.

The invention provides an electric control communication system and method for a sewing machine, electronic equipment and a medium. The system comprises master electric control equipment, a plurality of pieces of slave electric control equipment and a plurality of pieces of expansion electric control equipment, the switching device is provided with a communication master node and communication slave nodes of which the number corresponds to that of the slave electric control equipment; the communication master node is in communication connection with a master electric control device through an asynchronous serial port communication protocol, and each communication slave node is in communication connection with a corresponding slave electric control device through the asynchronous serial port communication protocol to form a serial port communication loop; the expansion device is provided with expansion slave nodes corresponding to the expansion electric control equipment in number; each communication slave node and each extension slave node are in communication connection with the communication master node through a CAN communication protocol to form a CAN communication loop; and the CAN communication loop and the serial port communication loop perform data interaction based on a data mapping mechanism. The problems that an existing sewing machine electric control system is poor in equipment expansibility and insufficient in data transmission real-time performance in the aspect of communication are solved.

This invention relates to the field of data storage technology and discloses a hardware optimization method for a test project. The method includes: a host computer (PC); a System-on-Chip (SOC) module, which is the control core of the entire test system and enables communication within the system; an MCU control module, which communicates asynchronously with the host computer via a UART interface and simultaneously exchanges high-speed data with the main SOC module via an SPI interface, thus facilitating communication between the host computer and the SOC module and controlling the SOC module's power supply; and a DDR module, whose DDR pin is connected to the MCU control module, allowing the MCU control module to perform current testing on the DDR module. This invention improves test coverage, signal integrity, and test efficiency.

The invention provides an asynchronous serial communication method and system, and the method comprises the steps: a master station pulls down an initialization signal, and transmits the initialization signal to each slave station; when the slave station detects that the initialization signal is lowered, the slave station communication baud rate is initialized, and a low-level state signal is output; when the master station detects a low-level state signal of the slave station, the initialization signal is pulled up, and a pulse with a predetermined baud rate is sent to each slave station through a data line; if the slave station detects that the fixed-frequency pulse received by the data line is kept stable within a preset duration, it is judged that the slave station communication baud rate is confirmed successfully, a next-level slave station state signal is obtained, and if the next-level slave station state signal is in a high level, the current slave station state signal is set to be in a high level; and the master station detects that the state line signals of the slave stations are high levels, judges that all the slave stations are successfully configured, and starts communication. Through the scheme, the Baud rate configuration efficiency of asynchronous serial communication can be improved, the Baud rate configuration time is shortened, and manpower and material resources are saved.

The invention provides a small laser projection simulation system, and belongs to the field of laser guided weapon testing. The problems that a traditional laser projection diffuse reflection device is poor in light spot uniformity, single in interaction mode, large in weight and large in needed space are solved. The system comprises a main control board which is provided with a multipath asynchronous serial communication interface; the laser, the light spot adjusting assembly and the fast reflecting mirror assembly are respectively communicated with the main control board through the asynchronous serial communication interface; the laser emits light, the light spot size is adjusted through the light spot adjusting assembly, the angle is adjusted through the fast reflecting mirror assembly, and the light is projected to the diffuse reflection screen. The device is mainly used for testing laser guided weapons.