202 results about "Asynchronous serial communication" patented technology

The invention relates to a modularized multi-level converter sub-module control and protection method. The control and protection method comprises the following processing modes: in four control models of a sub-module, executing different control and protection logics by using a sub-module controller; generating a sub-module internal interface output signal, detecting an input signal and diagnosing a plurality of faults; executing control and protection actions by using the sub-module controller according to an action priority level; detecting the voltage of an energy storage capacitor C by using the sub-module controller; and performing asynchronous serial communication between the sub-module controller and a valve-based controller. In the method, a complete and intelligent control and protection scheme is designed aiming at the structure of the modularized multi-level converter sub-module, the coordinated control and protection of the overall sub-module can be realized, so that the stable and reliable operation of the sub-module in a converter and the coordinated matching with an overall control and protection system of the converter are ensured.

The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream. An interrupt is sent to the slave device by withholding the data clock signal for a predetermined amount of time. Upon receipt of the interrupt, the slave device monitors the data stream for the presence of the preamble code word. Upon detection of the preamble code word, data transmitted by the codec is again enabled.

The invention discloses a three-dimensional attitude measurement device for a tunneling construction guidance system, which belongs to a positioning measurement device and aims to solve the problems that the prior three-dimensional attitude measurement device has higher requirement on the light intensity and is not accurate to the processing of pulsed light signals so as to simplify the installation and use of equipment. A prism, a lens, a CCD camera and an inclinometer are sequentially arranged on a light path along the axial direction in a machine case of the device, and output signals of the CCD camera are sent to a computer through a gigabit network cable; and output signals of the inclinometer are sent to the computer through an asynchronous serial communication interface. The device has small volume, simplifies the operation, and directly utilizes infrared rays of a total station instrument to focus through the lens to project on the photosensitive surface of the CCD camera to produce a photosensitive signal, the photosensitive signal is processed to obtain deflection angle data of incident light, and the deflection angle data are output to an external computer along with inclination angle data measured by the inclinometer. The device is mainly used for attitude measurement during the construction process of a shield machine and obtains a pitching angle, a rolling direction angle and a horizontal deflection angle of a shield in a real-time mode.

An embedded gateway for WiFi and ZigBee wireless network protocol conversion belongs to the wireless communication network technology field, the embedded gateway comprises a microprocessor, a system bus and a peripheral circuit which is connected with the microprocessor, and the peripheral circuit comprises a Flash memory, a SDRAM memory, an asynchronous serial communication port, an Ethernet interface, a JTAG interface, a USB interface, a USB wireless network card, a GPIO interface and a ZigBee wireless transceiving module. The embedded gateway has the advantages of low cost and small size, and the embedded gateway is applicable to mass production and fixed-point layout in project development; the data processing speed is fast; the reliability is high, the functions are powerful; the power consumption is lower and the embedded gateway can be used for a long time under special circumstances. The embedded gateway can realize the protocol conversion and data forwarding between the wireless ZigBee network and the wireless WiFi network, thereby realizing the interoperability between the two wireless networks.

A communication system and a method for operating a communication system, the communication system having a CAN bus and at least two devices connected with the aid of the CAN bus. Such a device has a CAN control unit, an asynchronous, serial communication (ASC) interface unit, and a switch. The CAN control unit is suitable for transmitting, in a first transmission mode, CAN data frames over the CAN bus with the aid of a first physical protocol. The asynchronous, serial communication interface unit or ASC interface unit is suitable for transmitting, in a second transmission mode, ASC data frames over the CAN bus with the aid of a second physical protocol. The switch is designed for switching over between the first transmission mode and the second transmission mode as a function of at least one agreement effective between the device and at least one other device.

The invention belongs to the technical field of digital communication, and particularly relates to a method for automatically detecting asynchronous serial port communication protocol on the basis of level sampling. The method includes firstly sampling level signals of asynchronous serial port communication, and detecting asynchronous serial port communication Baud rate according to the relation of the asynchronous serial port communication Baud rate and average time span of a single low level of the sampled signals; secondly, determining data frame bit digits and data frame positions of target signals which are the detected level signals by Baud rate by means of stop bit correlation matching algorithm; thirdly, analyzing in-frame data and inter-frame bit distance to determine data bit digits, checking manners and stop bit digits of the target signals; and finally determining a data coding manner of the target signals by Bayes policy method on the basis of the minimum error rate. The method can be applicable to communication protocol detection of communication and data transmission equipment utilizing the asynchronous serial port communication protocol.

The present invention provides a multi-serial port extension method based on FPGA and TL16C554A. The method employs the following hardware: an FPGA, n TL16C554A chips, and n serial port level conversion chips. The FPGA is connected to a DSP via a data bus, an address bus and a control bus. The FPGA acts as an asynchronous memory of the DSP processor, and implements communication with the DSP, time sequence driving of the TL16C554A chip, chip selection decoding and interrupt decoding. The TL16C554A chip is a management unit of asynchronous serial communication, and comprises four serial port communication management units and is capable of converting parallel data into four paths of serial outputs, can implement transmission and reception management of the four serial ports, and can simultaneously achieve communication with 4n devices. The method according to the present invention is a multi-serial port extension method which occupies less processor address space and fewer interrupt resources, has a high reliability, and is simple to transplant.

A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.

The invention relates to an asynchronous wireless communication system, such as a UMTS system. The various base stations of an asynchronous wireless communication system do not typically have known timing offsets Tb(i), and these timing offsets vary with time. The invention allows the calculation of the difference dTb(i,j) between timing offsets Tb(i), Tb(j) for pairs of base stations B(i), B(j), using the timing of signals received by one or more wireless communication units. Having eliminated the timing offsets between the base stations as a variable, geo-location techniques from synchronous networks may then be used to locate wireless communication units in the asynchronous wireless communication system.

The invention relates to a power distribution transformer monitoring terminal and a method for calculating the current complex power precision thereof, a three-phase voltage is connected with the signal input end of a signal conditioning circuit by a voltage transformer and a three-phase current is connected with the signal input end of the signal conditioning circuit by a current transformer respectively, the signal output end of the signal conditioning circuit is connected with an analog to digital conversion module in a digital signal processor; the digital signal processor is respectively connected with two asynchronous serial communication interfaces UARTA and UARTB by an external expansion interface chip interactively, the UARTA is interactively connected with an RS485 interface by an electrical level switching chip, and the UARTB is interactively connected with an electric-power line low voltage carrier wave meter reading module. The measuring precision of the three-phase current and the complex power is increased by adopting the fast Fourier transform FFT algorithm. The functions of measuring, monitoring, communication and meter reading are integrated into one body and the precision of calculating the current and the complex power of the power distribution transformer monitoring terminal is increased.

The invention relates to a fiber data transmission method based on an asynchronous communication mode. According to the method, an employed high speed data transmission circuit is realized by employing an internal function design mode of an FPGA chip, the realized logic functions comprise data generation, digital clock management, clock compensation, data detection, asynchronous FIFO caching based on Gray code counting and Aurora protocol logic control, and the functions of data generation, digital clock management, clock compensation, data detection and Aurora protocol logic control are realized by employing an FPGA standard setting mode. The method is characterized by realizing asynchronous FIFO caching based on Gray code counting, clock network generation and a transmission circuit function. The method employs a fiber data transmission method combining the asynchronous FIFO caching based on the Gray code counting mode with an Aurora protocol, and thereby data transmission accuracy is improved.

The invention relates to an MIMO channel simulator control method and the implementing device thereof, relating to wireless communication simulating system. And it comprises DSP algorithm module, synchronous dynamic memory, flash memory, asynchronous serial communication module and level converting module, and considers both time and frequency fading and selective space fading, and considers corresponding selective frequency fading by PDP, corresponding selective time fading by DPSD and corresponding selective space fading by PAS in the model establishing course. And the simulator has low price and simple structure.

A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.

A measuring device for testing thermal flow density under adverse circumstances consists of heating element, probe core, water pipe, industrial thermocouple set at thermal flow incoming end, water in and water out head connected through to cavity formed by water pipe and probe, cooling water channel in heating element, water incoming element and water outgoing element connected separately to internal channel and external channel of heating element, thermocouple signal collection unit being used to transmit its signal to computer through signal line according to RS-485 asynchronous serial communication rule .

In a handover from an asynchronous radio network to a synchronous system, long code state information and activation time are transmitted. The method of transmitting long code state information and activation time includes the step of acquiring handover-related information from a neighboring synchronous system by the asynchronous radio network. In the handover, the synchronous system transmit a first message including activation time information and long code state information to the mobile station by the asynchronous radio network and after receiving the activation time information and the long code state information, makes use of the long code state information based on the activation time information by the mobile station.

The present invention discloses an asynchronous serial communication controller, which includes over three asynchronous serial communication controller internal control logics, a sending port, a receiving port, a sending objective register and a receiving source register, which correspond with each asynchronous serial controller, and a main controller. The main controller processes the information frames, which are received from each asynchronous serial port, judges whether the information frame type is instruction frame or data frame and processes the information correspondingly. If the information frame is an instruction frame, the main controller operates on a relative register according to the contents of the instruction frame. If the information frame is a data frame, the main controller sends the data frame contents at a set data format and rate from the set serial port according to contents of relative registers. The present invention has the following advantages that the present invention supports several asynchronous serial interfaces to communicate directly and mutually at a high speed, improves system efficiency and is easy to use.

This invention relates to a GPS recorder with MP3 audio, video recording and remote sending, including a running recorder substrate, which has a CPU module, GPRS communication module and links GPS satellite positioning module and car power. Its character is that CPU module connects with digital multimedia unit through high-speed serial lines, and the digital multimedia unit includes CPU module, digital analog converters, data memory, MP3 / image data memory, program memory, USB chip, USB ports, audio output ports. CPU module connects audio output port through digital analog converter, and GPRS for outside sending-receiving through UART asynchronous serial communication, to make the recorder realize MP3 music, voice, video, and recording digital signal transmission of remote images.

The speed of asynchronous serial communications is detected by determining a duration of a data bit within an asynchronous data stream. The duration of the data bit is used to generate a clock frequency. The clock frequency is used to clock data from the asynchronous data stream into a register. The clocked data is processed according to an error indication.

The invention discloses a serial asynchronous communication data transmission method, and aims to provide a method which is intuitive and simple in structural model, short in design flow, distinct in procedure level and high in reliability, and can ensure the instantaneity of communication transmission data on communication time series and data frame formats. The serial asynchronous communication data transmission method is implemented through the following technical scheme and comprises the steps of adopting an upper computer micro-control chip as an upper computer for asynchronous serial communication, adopting a lower computer micro-control chip as a lower computer for asynchronous serial communication, and connecting the upper computer and the lower computer through a TTL (Transistor-Transistor Logic)/serial signal conversion circuit to form a serial asynchronous communication data transmission device; arranging serial asynchronous communication data transmission program software formed by a serial data receiving processing module, a serial data transmission module and a timer T module in the upper computer micro-control chip and the lower computer micro-control chip; transmitting serial data frame information to transmit buffers of the upper computer and the lower computer in a time-division way; assigning the real data frame to a buffer array Ai through a receive buffer; storing an array word string consistent to a communication frame protocol into a buffer array Bi.

The invention discloses an all-purpose asynchronous serial communication controller. The controller comprises a bidirectional IO processing module, a PCI secondary controller, an interior bus interface, interrupt management, and 1 to 8 channels UART control module, wherein the bidirectional IO processing module is used for connecting an exterior bus signal with a signal of the PCI secondary controller and merging the corresponding input output signals of the PCI secondary controller into a bidirectional signal of the PCI bus. The application coverage of the invention is wider than the controller of four channels. The depth for transceiving FIFO of each UART channel is 512 bytes and the processor access frequency is at least reduced by 4 times of the industrial controller. The controller supports sharing the 485 bus communication and receiving the enable control and is flexible to use. The processor interface is PCI bus, the integrated level is high which is beneficial to integrate a system, and the data throughput rate is high, and the highest data throughput rate reaches to 132MB/s.

A serial interface apparatus includes a first signal terminal sharing a data transmitting terminal and a second control signal terminal, a second signal terminal sharing a data receiving terminal and a first control signal terminal, and first to fourth buffer amplifiers. Upon receiving two types of second control signals different from each other from the other side apparatuses after transmitting the first control signal to the other side apparatus, the controller executes half-duplex data communication using the two signal terminals by transmitting the serial data signal to the other side apparatus via the first signal terminal, transmitting to the first signal terminal a serial data signal indicating a notice of termination upon end of the serial data signal to be transmitted, and judging as a data communication termination upon reception of the second control signal from the other side apparatus in response to the transmission of the serial data signal.

Provided is a high-precision phase and frequence measuring system. An input signal conditioning circuit in the system respectively converts a channel A signal, a channel B signal and a reference clock signal from external input into pulse signals and sends the pulse signals to a field programmable gata array (FPGA) circuit. The FPGA circuit makes a rough count measurement on the time interval between the treated channel A signal and the channel B signal and generates two interpolating pulses at the beginning and the end of the time interval and respectively outputs two interpolating pulses into an integral analog extension circuit. Two integral pulses sent back from the integral artificial extension circuit are received, a count measurement on the pulses which are sent back are respectively made, combining the count measurement and delay correction parameters to obtain phases and frequencies of the A signal and the B signal through calculations, and the phases and frequencies are sent to a host computer through an asynchronous serial communication circuit. The integral extension circuit forms an integral voltage according to the interpolating pulses, compares, reforms and sends the integral voltage to the FPGA circuit. The asynchronous serial communication circuit is used for communicating with host computer serial ports and a parameter storing circuit is used for storing delay correction parameters.

A method includes receiving at a host device a first communication associated with a transaction from at least one electronic device included in a set of electronic devices. The host device includes at least a memory, a processor, and a database. The first communication received at a first time and via a first communication mode. The method includes sending a response to the first communication at a second time after the first time and independent of the first time. The host devices receives a second communication associated with the transaction from the at least one electronic device at a third time. The first communication, the response to the first communication, and the second communication are displayable in a persistent record of the transaction regardless of a difference between the first time and the third time.

An asynchronous serial communication method and the apparatus including a sender transmitting a one bit of serial data by firstly making a signal transition on the data line, secondly putting the one bit of serial data on the data line after a predetermined time T1 yet before another predetermined time T1+T2, and a receiver receiving the one bit of serial data by firstly detecting the signal transition on the data line and secondly capturing the one bit of serial data after a predetermined time T3 (where T3>T1+T2).