Multi-serial port extension method based on FPGA and TL16C554A

A technology of TL16C554A and expansion method, applied in the field of multi-serial port expansion, can solve the problems of loss of serial port sending and receiving data, low serial port reliability, and no consideration of serial port expansion chip timing drive, etc., and achieves high real-time performance, high reliability and flexibility. changing effect

Active Publication Date: 2015-08-26
哈尔滨工业大学(鞍山)工业技术研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method only considers the logic of chip selection and interrupt, and does not consider the timing drive of the serial port expansion chip. Often the timing does not meet the requirements of the serial port expansion chip, resulting in the loss of serial port sending and receiving data, and the reliability of the extended serial port is not high.

Method used

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  • Multi-serial port extension method based on FPGA and TL16C554A
  • Multi-serial port extension method based on FPGA and TL16C554A
  • Multi-serial port extension method based on FPGA and TL16C554A

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Embodiment 1

[0059] Technical indicators of this expansion method:

[0060] DSP processor: TMS320C6713B

[0061] FPGA: EP2C50F484I8

[0062] Serial expansion chip: TL16C554A

[0063] Serial port level conversion chip: MAX3490

[0064] If the DSP processor TMS320C6713B is used in the multi-sensor real-time data acquisition system (here the processor is DSP as an example, other types of processors can choose the corresponding signal line, the same below), since the processor itself does not have a serial port, the serial port When the expansion chip expands multiple serial ports, the multi-serial port expansion method invented by this patent includes FPGA, TL16C554A, serial port level conversion chip, and the functional block diagram is as follows figure 1 shown.

[0065]Among them, FPGA mainly completes the communication with DSP, as well as the timing drive, chip selection decoding and interrupt decoding of TL16C554A. TL16C554A is a management unit for asynchronous serial communicatio...

Embodiment 2

[0109] like Image 6 It is an implementation mode for expanding 32 serial ports outside the DSP processor. Among them, FPGA chooses EP2C50F484I8, which has 294 available IOs, which meets the 184 IOs required for the connection between 8 TL16C554A and FPGA and the 29 IOs required for the connection between DSP and FPGA. The clock frequency of the FPGA crystal oscillator is 40MHz.

[0110] FPGA occupies 5 double-byte addresses in the corresponding address space of DSP chip select signal CE3, 0xB0000000, 0xB0000002, 0xB0000004, 0xB0000006 and 0xB0000008, which are respectively used for the control word CTRL_WORD_C54 pointer, the sending data DATA_TO_C54 pointer, the receiving data DATA_FROM_C54 pointer, and two self- Define the interrupt flag register pointers C54_INT_REG0 and C54_INT_REG1. The FPGA completes the decoding of these three address pointers according to CE3, the lower 8-bit address line, the DSP read signal line, and the DSP write signal line, and reads data from t...

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Abstract

The present invention provides a multi-serial port extension method based on FPGA and TL16C554A. The method employs the following hardware: an FPGA, n TL16C554A chips, and n serial port level conversion chips. The FPGA is connected to a DSP via a data bus, an address bus and a control bus. The FPGA acts as an asynchronous memory of the DSP processor, and implements communication with the DSP, time sequence driving of the TL16C554A chip, chip selection decoding and interrupt decoding. The TL16C554A chip is a management unit of asynchronous serial communication, and comprises four serial port communication management units and is capable of converting parallel data into four paths of serial outputs, can implement transmission and reception management of the four serial ports, and can simultaneously achieve communication with 4n devices. The method according to the present invention is a multi-serial port extension method which occupies less processor address space and fewer interrupt resources, has a high reliability, and is simple to transplant.

Description

technical field [0001] The invention relates to a multi-serial port expansion method based on FPGA and TL16C554A. Background technique [0002] For systems with high real-time requirements for multi-sensor (often more than 4) data acquisition, since the number of serial ports of the processor is often less than 4, in order to realize the communication between the processor and multiple sensors through the serial port, it is necessary to expand the serial port of the processor . [0003] There are generally two ways to expand the serial port: the first is to use the software simulation method to expand the serial port, that is, in the programmable digital logic chip such as PLD, use the software to simulate the function of sending and receiving of the serial port to realize the serial port expansion. This method has the advantages of less resources occupied by the I / O port of the microprocessor and simple circuit design. However, the serial port logic is complex to simulate ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G06F13/42G06F13/24
CPCG06F13/24G06F13/4068G06F13/4282G06F2213/0002G06F2213/2418
Inventor 贾建峰王常虹石峰王贺年
Owner 哈尔滨工业大学(鞍山)工业技术研究院
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