90results about "Delay compensation" patented technology

The invention discloses a high-voltage level conversion circuit with a symmetric pulse current structure, which belongs to the technical field of integrated circuits and comprises a level conversion module, a symmetric pulse current auxiliary module and a latch output module. According to the level conversion module, the defect that in the prior art, when the voltage of a power supply jumps rapidly, a circuit may be triggered by mistake is overcome, and the immunity of the circuit is improved. According to the symmetrical pulse current auxiliary module, the defect that transmission delays at the rising edge and the falling edge of an input signal are asymmetric in the prior art is overcome, so that the symmetrical pulse current auxiliary module keeps high transmission delay symmetry while ensuring a high transmission speed; and the problem of possible distortion of digital signal input and output in a high-speed circuit is effectively suppressed.

The invention discloses an anti-single event upset latch circuit structure with fewer sensitive nodes. The anti-single event upset latch circuit structure comprises a clock filter circuit, a delay filter circuit, a latch circuit and a stacked inverter circuit. The clock filter circuit is used for filtering single-particle transient pulses at a clock end and providing clock signals for the latch circuit. The delay filter circuit is used for filtering single-particle transient pulses of a data end and providing input signals for the latch circuit. And the latch circuit is used for realizing data transmission and latch, and maintaining a correct signal output state and level correction after single-particle radiation in a latch state. The stacked inverter circuit is used for providing an inversion signal. The designed latch circuit can realize single-particle transient reinforcement and single-particle transient pulse filtering, has few circuit sensitive nodes, is good in reinforcement effect, and is simple and easy to realize.

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

The invention provides a novel time offset calibration circuit and method, and belongs to the technical field of analog ICs. Comprising a buffer A and a buffer B which are connected in sequence, the output node of the buffer A is grounded through a capacitor, the output node of the buffer A is grounded through a resistor and a current source set controlled by a switch, and the output end of the buffer B is connected with a time offset detection circuit. According to the clock offset calibration circuit provided by the invention, a novel topological structure is adopted, and the calibration range of time offset can be greatly expanded without a lengthy buffer chain, so that the introduction of noise is reduced. The time offset adjustment step length of the circuit structure is not limited by the minimum size of the capacitor, and has no extremely high matching requirement on the capacitor. The time offset calibration with a small step length can be realized by controlling the extracted current, and the calibration precision is ensured while the calibration range is improved.

The present disclosure provides a pulse trigger and a phase discriminator. The pulse trigger includes a logic module, a first input stage module, and a second input stage module; the circuit structures of the first input stage module and the second input stage module are the same; the logic module includes a first charging path corresponding to the positive terminal signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive terminal signal of the differential signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; the logic module is respectively connected to the first input stage module and the second input stage module. When the first clock signal is a rising edge signal, the logic module conducts based on the input signals of the first input stage module and the second input stage module, and the inverted output terminal of the pulse trigger outputs a high-level signal. By accelerating the charge and discharge stages of the pulse trigger, shortening the dead time, and improving the resolution of the pulse trigger, static errors are eliminated.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

The invention provides an ultra-high-speed level conversion circuit of a digital circuit, and relates to the technical field of level conversion of DC-DC application, and the ultra-high-speed level conversion circuit comprises a DC-DC high-side driving module which is used for ultra-high-speed level conversion and comprises a high-level converter. A low-voltage input signal hsinlv drives cfly1 and cfly2 through inverters inv1 and inv2, so that driving delay below 50pS can be easily realized, transmission delay after cfly1 and cfly2 bootstrap can be ignored, the driving delay from inhv and inphv to output hsinhv is driving delay of a logic gate and can be easily below 50pS, delay from the low-voltage input signal hsinlv to a high-voltage output signal hsinhv is transmission delay between digital gates, and the transmission delay between the digital gates is greatly reduced. And the transmission delay below 100pS can be easily realized.

The invention discloses a burr filtering circuit, method and device, a medium and a program product, and the burr filtering circuit comprises a first time delay circuit which is used for delaying an input signal by a time delay width; the first logic gate circuit is used for filtering high-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second logic gate circuit is used for filtering low-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second delay circuit is used for delaying the input signal by two delay widths; the third logic gate circuit is used for ensuring that the signal with the length greater than two delay widths is not filtered; and the fourth logic gate circuit is used for outputting a target serial signal, and the target serial signal is a signal obtained by filtering high-level burrs and low-level burrs of which the widths are less than or equal to the delay width of the input signal and delaying for one delay width. The burr filtering circuit provided by the embodiment of the invention is simple in circuit structure, small in size, easy to change in filtering width and low in output delay.

Embodiments provide a power supply switching circuit, which generates a first control signal jointly by utilizing a first input signal and a first drive signal opposite in phase to a second control signal, and generates the second control signal jointly by utilizing a second input signal and a second drive signal opposite in phase to the first control signal, such that time (i.e., overlap time) required for simultaneously turning on or off a first output subcircuit and a second output subcircuit is greatly reduced or even eliminated, effective output of an output node is implemented, and reliability of a device is improved. Furthermore, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power supply switching circuit is simple and reliable in control logic and is insensitive to process, which further improves the reliability of the device.

The invention discloses a time delay circuit, which comprises a time delay module used for carrying out transmission time delay on input logic data, the time delay module comprises at least two time delay units which are connected in series, each time delay unit comprises a phase inverter and a capacitor, the input end of the phase inverter receives an input signal of the time delay unit, and the output end of the phase inverter receives an output signal of the time delay unit. The output end of the phase inverter provides an output signal of the time delay unit, the first end of each capacitor is connected with the output end of the phase inverter, the second end of each capacitor receives control voltage, and the control voltage generation module is used for adjusting the control voltage provided for each capacitor according to the value of the input logic data so as to control the time delay unit. According to the time delay circuit, the capacitance value of each capacitor is adjusted, so that the time delay circuit can perform different transmission delays on different logic data, and a time difference with a determined proportion is formed between the two kinds of logic data, so that specific synchronous or asynchronous requirements are met.

The embodiment of the invention provides a delay compensation method for a configurable peripheral input and output pin and a related product. The method comprises the steps that an input and output delay adjustment circuit detects whether a delay compensation requirement for the configurable peripheral input and output pin exists or not currently; and when the configurable peripheral input / output pin has a delay compensation requirement, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin. According to the embodiment of the invention, the delay of the input and output pins of the configurable peripheral can be adjusted through the input and output delay adjusting circuit, so that the flexibility of wiring design of a user circuit board can be ensured, and the reliability of data communication with the high-speed peripheral can be improved.

The invention provides a pulse trigger and a phase discriminator. The pulse trigger comprises a logic module, a first input stage module and a second input stage module, the circuit structures of the first input stage module and the second input stage module are the same; the logic module comprises a first charging path corresponding to a differential signal positive end signal of the first clock signal and a second charging path corresponding to a differential signal positive end signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and a phase difference exists between the second clock signal and the first clock signal; the logic module is connected with the first input stage module and the second input stage module, and when the first clock signal is a rising edge signal, the logic module conducts the reverse output end of the pulse trigger to output a high level signal based on the input signals of the first input stage module and the second input stage module. By accelerating the charging and discharging stages of the pulse trigger, the dead time is shortened, the resolution of the pulse trigger is improved, and static errors are eliminated.

The application discloses a low-latency driving circuit and a driving device. The low-latency driving circuit comprises an output transistor, an output terminal of which is connected to or serves as a driving output terminal of the driving circuit; and a first control transistor, an input terminal of which is connected to a first voltage level, and an output terminal of which is connected to a control terminal of the output transistor; wherein when the driving circuit switches to an open output, the first control transistor is turned on and the first voltage level is applied to the control terminal of the output transistor to raise the voltage of the driving output terminal. The low-latency driving circuit provided by the application can reduce the delay of output response under the premise of providing adjustable driving circuit output, so as to adapt to high-precision and fast-response application scenarios.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

The invention discloses an input and output circuit, which comprises an input and output module, a high selection module, a control module and a protection switch module, and is characterized in that the input and output module comprises a pull-up PMOS (P-channel Metal Oxide Semiconductor) tube and a logic driving module. The high selection module compares the PAD end voltage with the power supply voltage and outputs the higher voltage as the substrate control signal end voltage, so as to ensure that the substrate voltage of the pull-up PMOS tube is not lower than the PAD end voltage; meanwhile, a transmission gate switch structure in the related technology is replaced by a structure that an inverter is connected with a PMOS in series, a control module generates a protection control signal based on the working state of a power supply voltage end, and a logic protection unit and a driving protection unit in a protection switch module are used for respectively controlling a current path of a logic unit and the working state of a pull-up PMOS tube. Therefore, the current backflow phenomenon is prevented, and the chip and connection equipment are protected.

The invention discloses a turn-on time control circuit, a circuit board and electronic equipment, and belongs to the field of electronic circuits, and the turn-on time control circuit comprises a conversion module, a current mirror module, a generation module and a control module. The conversion module outputs a related first current according to an external load input voltage, and the current mirroring module mirrors the first current to generate a second current. The generation module comprises a charging unit and a charging control unit, the charging unit receives the second current for charging, and the charging control unit controls the charging process according to the voltage at the two ends of the charging unit and the external load output voltage and ensures that the charging voltage is not zero. The control module adjusts the charging time of the charging unit through the external output reference voltage and the output voltage so as to control the conduction time of the current mirror image module, the undershoot voltage of the output voltage when the load transients can be reduced, and the stability of the power supply in a high-load state is improved.

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.

The invention provides an asynchronous subthreshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting at least one basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the series connection number of a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit does not exceed a preset series connection number upper limit; a sensitive amplifier-transmission transistor logic circuit directly connected with the input end of the trigger unit is determined from the first sub-threshold logic circuit; replacing the sense amplifier-pass transistor logic circuit with an asynchronous detection sense amplifier-pass transistor logic circuit; and deleting the clock circuit in the first sub-threshold logic circuit to form a second sub-threshold logic circuit. Signal weakening is reduced, time delay is reduced, the working frequency of the sub-threshold logic circuit is improved, and a transmission transistor network is adopted to support circuit units with unfixed logic functions.

The invention provides a burr eliminating circuit, a burr eliminating method and electronic equipment. The burr eliminating circuit comprises a delay circuit, a trigger and a control circuit, the control circuit adjusts a control signal according to a first signal and a second signal, so that the control signal controls the trigger to work in a reset mode or a sampling mode, the trigger working in the reset mode does not sample the first signal, the trigger continuously outputs low level, and the trigger does not output low level. The trigger working in the sampling mode samples the first signal, and starts to output a high level from the rising edge of the second signal until the falling edge of the second signal appears, so that the signal section with the pulse width smaller than the delay time of the delay circuit in the first signal can be filtered out through the arrangement of the trigger; the signal segment with the pulse width larger than or equal to the delay time of the delay circuit in the first signal can be normally sampled and output by the trigger, so that random burrs of the first signal in the transmission process can be filtered out, and it is guaranteed that the signal is not distorted.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven. The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

The invention discloses a frequency-voltage conversion circuit, which realizes the function of generating a two-phase switch control signal with a phase difference by multiplexing a clock input signal representing frequency information in front of a frequency dividing circuit and performing simple combinational logic on the clock input signal and a frequency dividing signal. Therefore, the influence of process, voltage or temperature fluctuation on the stability of the circuit is avoided.

The invention discloses a delay circuit comprising a first bias unit used for generating a first bias current; the second bias unit is used for generating bias voltage; the current mirror image unit is connected between the first bias unit and the second bias unit and is used for generating an output voltage based on the first bias current and the bias voltage; and the delay unit comprises a plurality of cascaded inverters and is used for delaying the input clock signal based on the output voltage to generate a delayed clock signal. The first bias unit and the second bias unit are arranged to provide the output voltage for the delay unit, and the influence of the current mirror image unit on the output voltage is counteracted with the change of the process corner and the environment temperature, so that the output voltage can be changed with the change of the process corner and the environment temperature of the delay circuit; the delay clock signal is prevented from changing along with the process corner and the temperature, and meanwhile, the delay clock signal is prevented from changing along with the power supply voltage, so that the delay change of the delay circuit is reduced.

The invention relates to the technical field of latches, and discloses a high-performance low-overhead four-point reinforced latch based on dual modular redundancy, which comprises an input module, a storage module L1 and a storage module L2, the storage module L1 and the storage module L2 are connected with the input module, and the storage module L1 and the storage module L2 are connected with an output module; and the input module comprises a transmission gate TG1-a transmission gate TG10 which are connected with the storage module L1 and the storage module L2. According to the method, internal four-node overturning can be completely tolerated, and meanwhile, the method has a relatively high four-node overturning self-recovery rate and relatively high reinforcing performance and reliability; a double-input C unit stacking structure is adopted, the leakage power consumption is greatly reduced, and the clock control double-input C unit is utilized, so that the dynamic power consumption is reduced; only one transmission gate is arranged from the input end to the output end in a transparent mode, so that the latch has low time delay and can be widely applied to the fields of aerospace and the like with high requirements on reliability and low power consumption of the latch.

To provide a semiconductor device capable of increasing speed of switching between on and off of a high frequency switch.SOLUTION: A semiconductor device of an embodiment includes: transistors M1 and M2 for respectively supplying a voltage Vp and a voltage Vn to a first end; transistors M3 and M4 for respectively supplying a power supply voltage and a ground voltage to the first end; a level shifter LS1 for converting a signal EP and outputting a signal RGP; and a second level shifter LS2 for converting a signal EN and outputting a signal RGN. When outputting the voltage Vp from the first end, the semiconductor device supplies the power supply voltage from the transistor M3 to the first end according to the signal RGN, and then supplies the voltage Vp from the transistor M1 to the first end according to the signal RGP. When outputting the voltage Vn from the first end, the semiconductor device supplies the ground voltage from the transistor M4 to the first end according to the signal RGP, and then supplies the voltage Vn from the transistor M2 to the first end according to the signal RGN.SELECTED DRAWING: Figure 2

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: transistors (M1) and (M2) that supply a voltage (Vp) and a voltage (Vn) to a first terminal, respectively; transistors (M3) and (M4) for supplying a power supply voltage and a ground voltage to a first terminal, respectively; a level shifter (LS1) that converts the signal EP and outputs a signal RGP; and a second level shifter (LS2) that converts the signal EN and outputs a signal RGN. When the voltage Vp is output from the first terminal, the power supply voltage is supplied from the transistor M3 to the first terminal according to the signal RGN, and then the voltage Vp is supplied from the transistor M1 to the first terminal according to the signal RGP. When a voltage Vn is output from a first terminal, a ground voltage is supplied from a transistor M4 to the first terminal in accordance with a signal RGP, and then the voltage Vn is supplied from a transistor M2 to the first terminal in accordance with a signal RGN.

An integrated circuit (IC) device includes first and second dies. The first die includes a first transmit circuit, a first receive circuit, and a first circuit. The first transmission circuit transmits an output clock signal corresponding to the first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs a first signal corresponding to the input signal based on the input clock signal. The first circuit outputs a second signal corresponding to the first signal based on the first clock signal. The second die includes a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal, and a second transmitting circuit coupled to the first receiving circuit and transmitting an input signal and an input clock signal corresponding to the output clock signal to the first receiving circuit based on the output clock signal. The embodiment of the invention also discloses a method for operating the integrated circuit device.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

The present invention relates to the field of integrated circuit technology, and specifically to a high-voltage level shift circuit suitable for a GaN driver chip. The circuit converts a signal in a low-voltage domain into a signal in a high-voltage domain, and is characterized in that it includes a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch, and a signal maintenance module; the voltage-to-current signal module is used to convert a PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted by the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current to maintain the established signal state. This solution effectively solves the contradiction between power consumption, transmission delay, CMTI capability, and the ability to resist negative pressure of the switch node in the traditional level shift circuit.