35results about "Delay compensation" patented technology

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

The invention provides an ultra-high-speed level conversion circuit of a digital circuit, and relates to the technical field of level conversion of DC-DC application, and the ultra-high-speed level conversion circuit comprises a DC-DC high-side driving module which is used for ultra-high-speed level conversion and comprises a high-level converter. A low-voltage input signal hsinlv drives cfly1 and cfly2 through inverters inv1 and inv2, so that driving delay below 50pS can be easily realized, transmission delay after cfly1 and cfly2 bootstrap can be ignored, the driving delay from inhv and inphv to output hsinhv is driving delay of a logic gate and can be easily below 50pS, delay from the low-voltage input signal hsinlv to a high-voltage output signal hsinhv is transmission delay between digital gates, and the transmission delay between the digital gates is greatly reduced. And the transmission delay below 100pS can be easily realized.

The invention discloses a time delay circuit, which comprises a time delay module used for carrying out transmission time delay on input logic data, the time delay module comprises at least two time delay units which are connected in series, each time delay unit comprises a phase inverter and a capacitor, the input end of the phase inverter receives an input signal of the time delay unit, and the output end of the phase inverter receives an output signal of the time delay unit. The output end of the phase inverter provides an output signal of the time delay unit, the first end of each capacitor is connected with the output end of the phase inverter, the second end of each capacitor receives control voltage, and the control voltage generation module is used for adjusting the control voltage provided for each capacitor according to the value of the input logic data so as to control the time delay unit. According to the time delay circuit, the capacitance value of each capacitor is adjusted, so that the time delay circuit can perform different transmission delays on different logic data, and a time difference with a determined proportion is formed between the two kinds of logic data, so that specific synchronous or asynchronous requirements are met.

The application discloses a low-latency driving circuit and a driving device. The low-latency driving circuit comprises an output transistor, an output terminal of which is connected to or serves as a driving output terminal of the driving circuit; and a first control transistor, an input terminal of which is connected to a first voltage level, and an output terminal of which is connected to a control terminal of the output transistor; wherein when the driving circuit switches to an open output, the first control transistor is turned on and the first voltage level is applied to the control terminal of the output transistor to raise the voltage of the driving output terminal. The low-latency driving circuit provided by the application can reduce the delay of output response under the premise of providing adjustable driving circuit output, so as to adapt to high-precision and fast-response application scenarios.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

The invention discloses an input and output circuit, which comprises an input and output module, a high selection module, a control module and a protection switch module, and is characterized in that the input and output module comprises a pull-up PMOS (P-channel Metal Oxide Semiconductor) tube and a logic driving module. The high selection module compares the PAD end voltage with the power supply voltage and outputs the higher voltage as the substrate control signal end voltage, so as to ensure that the substrate voltage of the pull-up PMOS tube is not lower than the PAD end voltage; meanwhile, a transmission gate switch structure in the related technology is replaced by a structure that an inverter is connected with a PMOS in series, a control module generates a protection control signal based on the working state of a power supply voltage end, and a logic protection unit and a driving protection unit in a protection switch module are used for respectively controlling a current path of a logic unit and the working state of a pull-up PMOS tube. Therefore, the current backflow phenomenon is prevented, and the chip and connection equipment are protected.

The invention provides an asynchronous subthreshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting at least one basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the series connection number of a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit does not exceed a preset series connection number upper limit; a sensitive amplifier-transmission transistor logic circuit directly connected with the input end of the trigger unit is determined from the first sub-threshold logic circuit; replacing the sense amplifier-pass transistor logic circuit with an asynchronous detection sense amplifier-pass transistor logic circuit; and deleting the clock circuit in the first sub-threshold logic circuit to form a second sub-threshold logic circuit. Signal weakening is reduced, time delay is reduced, the working frequency of the sub-threshold logic circuit is improved, and a transmission transistor network is adopted to support circuit units with unfixed logic functions.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven. The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

The invention discloses a frequency-voltage conversion circuit, which realizes the function of generating a two-phase switch control signal with a phase difference by multiplexing a clock input signal representing frequency information in front of a frequency dividing circuit and performing simple combinational logic on the clock input signal and a frequency dividing signal. Therefore, the influence of process, voltage or temperature fluctuation on the stability of the circuit is avoided.

The invention relates to the technical field of latches, and discloses a high-performance low-overhead four-point reinforced latch based on dual modular redundancy, which comprises an input module, a storage module L1 and a storage module L2, the storage module L1 and the storage module L2 are connected with the input module, and the storage module L1 and the storage module L2 are connected with an output module; and the input module comprises a transmission gate TG1-a transmission gate TG10 which are connected with the storage module L1 and the storage module L2. According to the method, internal four-node overturning can be completely tolerated, and meanwhile, the method has a relatively high four-node overturning self-recovery rate and relatively high reinforcing performance and reliability; a double-input C unit stacking structure is adopted, the leakage power consumption is greatly reduced, and the clock control double-input C unit is utilized, so that the dynamic power consumption is reduced; only one transmission gate is arranged from the input end to the output end in a transparent mode, so that the latch has low time delay and can be widely applied to the fields of aerospace and the like with high requirements on reliability and low power consumption of the latch.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

This application provides a level shifter and a high-voltage half-bridge driver, belonging to the field of high-voltage power integrated circuit technology. The level shifter includes a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module. The first capacitor driving module generates a first pulse signal; the first pulse sensing module generates a fourth pulse signal; the second pulse sensing module generates a seventh pulse signal; the latch output module generates a target pulse signal and sends a feedback signal when the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. This application can reduce the signal transmission delay and power consumption of the level shifter and improve reliability.

The embodiment of the invention relates to a preset control loop for a PPG LED driver. According to an embodiment, a driver circuit for a light emitter in a photoplethysmography (PPG) system includes a main control loop having an operational amplifier and a transistor configured as a source follower. During the preset control stage, the preset circuit sets the output voltage of the operational amplifier to be a preset level. The switching circuit activates the preset circuit in a preset phase and activates the main control loop in a main control phase. Before the main control loop is activated, the preset circuit pre-regulates the gate voltage of the source follower transistor to be close to its threshold voltage. This improves startup performance by reducing delay and uncontrolled initial current while avoiding the need for amplifier trimming. The circuit can realize fast stabilization time and accurate control of short current pulse at a very low duty ratio, and is beneficial to PPG measurement accuracy and power efficiency in wearable health care monitoring equipment.

The embodiment of the invention provides a clock duty ratio correction circuit and a serializer / deserializer. The clock duty ratio correction circuit comprises a time delay module and an edge capture module, the time delay module comprises a plurality of controllable capacitors and is used for controlling the time delay of input clock signals by controlling the number of the controllable capacitors connected into a circuit and outputting two paths of time delay clock signals; the edge capturing module comprises four field effect transistors and is used for receiving the two paths of delay clock signals and performing edge selection on the two paths of delay clock signals through one path of control signal; an output clock signal is determined according to the edge selection result, and the duty ratio of the output clock signal is determined by the delay size of the two delay clock signals. According to the embodiment of the invention, the problem that a clock duty ratio correction circuit with higher calibration precision, lower power consumption and smaller integrated area is needed along with the increase of the communication rate in the prior art is solved.

An input / output (I / O) sensor for a multi-IC module. The I / O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An integrated circuit (IC) device includes a first die including a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The first circuit, in response to a first value of a first selection signal, outputs the second signal in response to a first edge of the first clock signal. The first circuit, in response to a second value different from the first value of the first selection signal, outputs the second signal in response to a second edge of the first clock signal.

Provided in the embodiments of the present disclosure are a clock duty cycle correction circuit, and a serializer / deserializer. The clock duty cycle correction circuit comprises: a delay module and an edge capture module. The delay module comprises a plurality of controllable capacitors, and is configured to control the delay magnitude of an input clock signal by controlling the number of capacitors among the plurality of controllable capacitors that are connected in a circuit, and to output two delayed clock signals. The edge capture module comprises four field effect transistors, and is configured to receive the two delayed clock signals and perform edge selection on the two delayed clock signals by means of a control signal, and determine an output clock signal on the basis of an edge selection result, wherein the duty cycle of the output clock signal is determined on the basis of the delay magnitude of the two delayed clock signals.

A multi-channel digital isolator includes a digital isolator (120B) and an interlock circuit (250). The isolator includes a transmitter (305) having a transmitter output, a receiver (310) having a receiver input and a receiver output, an isolation barrier (220) coupled between the transmitter output and the receiver input, and an output buffer (360A) having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping valid states between a first isolated signal and a complementary isolated signal. In some embodiments, the digital isolator further includes a dead time insertion circuit.

The invention discloses a frequency divider with adjustable output delay, and belongs to the field of integrated circuits. The frequency divider provided by the invention comprises an input module, a frequency division module and an output delay adjustment module. The input module is used for isolating an input clock signal from a pre-stage circuit and improving the swing of the input clock signal; the frequency division module is used for adjusting the frequency of the output clock signal; and the output delay adjusting module is used for adjusting the output delay time of the output clock signal.

According to the input and output circuit, a PAD end voltage and a power supply voltage are compared through a high selection module, the higher voltage is output as a substrate control signal end voltage, and it is ensured that the substrate voltage of a pull-up PMOS tube is not lower than the PAD end voltage; meanwhile, a transmission gate switch structure in the related technology is replaced by a structure that an inverter is connected with a PMOS in series, a control module generates a driving control signal based on the working state of the power supply voltage end, and a switch module controls the on-off state of a pull-up PMOS tube in response to the driving control signal, so that the phenomenon of current backflow is prevented, and a chip and connecting equipment are protected.

A time synchronization distribution input interface circuit and a delay compensation method, control module and computer readable storage medium thereof, wherein the time synchronization distribution input interface circuit comprises a level converter, a phase-locked loop (PPL) module and a control module, and further comprises a first selector and a second selector; the first selector is configured to input a reference measurement clock signal output by the PPL module to the level converter in a delay measurement phase and input a second pulse (1PPS) signal to the level converter in a working phase according to control of the control module; and the second selector is configured to output a signal output by the level converter to a second measurement end of the PPL module in the delay measurement phase and output the signal output by the level converter to a working end of the PPL module in the working phase according to control of the control module.

The present invention discloses a single-particle flip-resistant latch circuit structure with fewer sensitive nodes, comprising: a clock filter circuit, a delay filter circuit, a latch circuit, and a stacked inverter circuit. The clock filter circuit is used to filter single-particle transient pulses at the clock end and provide a clock signal to the latch circuit. The delay filter circuit is used to filter single-particle transient pulses at the data end and provide an input signal to the latch circuit. The latch circuit is used to realize data transmission and latching, and maintain the correct state and level correction of the output signal after single-particle radiation in the latched state. The stacked inverter circuit is used to provide an inverted signal. The designed latch circuit can realize single-particle transient reinforcement and single-particle transient pulse filtering, has fewer sensitive nodes in the circuit, has a good reinforcement effect, and is simple and easy to implement.

An integrated circuit (IC) device includes first and second dies. The first die includes a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The second die includes a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal, and a second transmitting circuit coupled to the first receiving circuit and transmitting to the first receiving circuit, based on the output clock signal, the input signal, and the input clock signal corresponding to the output clock signal.

The application relates to a power supply delay circuit and a hot plug device. The power supply delay circuit comprises a delay circuit, a first connecting end and a second connecting end. The delay circuit is connected with the first connecting end and the second connecting end. The first connecting end is used for connecting a power supply, and the second connecting end is used for connecting the power supply or a grounding end. The delay circuit is used for delaying the conduction of the power supply, so that the two power supplies are not conducted at the same time, or the power supply is conducted earlier than the grounding end, mutual interference between the power supplies is avoided, and the use reliability is improved.

The application discloses a conduction time control circuit, a circuit board and electronic equipment, and belongs to the field of electronic circuits. The conduction time control circuit comprises a conversion module, a current mirror module, a generation module and a control module. The conversion module outputs a related first current according to an external load input voltage. The current mirror module mirrors the first current to generate a second current. The generation module comprises a charging unit and a charging control unit. The charging unit receives the second current for charging. The charging control unit controls the charging process and ensures that the charging voltage is not zero according to the voltage across the charging unit and the external load output voltage. The control module adjusts the charging time of the charging unit by the external output reference voltage and the output voltage, thereby controlling the conduction time of the current mirror module. The application can reduce the undershoot voltage of the output voltage during load transients and improve the stability of the power supply under high load conditions.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

An apparatus comprises a first OR gate, a second OR gate, a first NAND gate, and a second NAND gate. The first OR gate comprises a first input terminal, a second input terminal, and an output terminal. The second OR gate comprises a first input terminal, a second input terminal, and an output terminal. The first NAND gate comprises a first input terminal coupled to the output terminal of the first OR gate. The first NAND gate also comprises a second input terminal coupled to the output terminal of the second OR gate. The second NAND gate comprises an output terminal coupled to the first input terminal of the second OR gate.