8results about "Delay compensation" patented technology

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

The embodiment of the invention relates to a preset control loop for a PPG LED driver. According to an embodiment, a driver circuit for a light emitter in a photoplethysmography (PPG) system includes a main control loop having an operational amplifier and a transistor configured as a source follower. During the preset control stage, the preset circuit sets the output voltage of the operational amplifier to be a preset level. The switching circuit activates the preset circuit in a preset phase and activates the main control loop in a main control phase. Before the main control loop is activated, the preset circuit pre-regulates the gate voltage of the source follower transistor to be close to its threshold voltage. This improves startup performance by reducing delay and uncontrolled initial current while avoiding the need for amplifier trimming. The circuit can realize fast stabilization time and accurate control of short current pulse at a very low duty ratio, and is beneficial to PPG measurement accuracy and power efficiency in wearable health care monitoring equipment.

An input / output (I / O) sensor for a multi-IC module. The I / O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An apparatus comprises a first OR gate, a second OR gate, a first NAND gate, and a second NAND gate. The first OR gate comprises a first input terminal, a second input terminal, and an output terminal. The second OR gate comprises a first input terminal, a second input terminal, and an output terminal. The first NAND gate comprises a first input terminal coupled to the output terminal of the first OR gate. The first NAND gate also comprises a second input terminal coupled to the output terminal of the second OR gate. The second NAND gate comprises an output terminal coupled to the first input terminal of the second OR gate.