56results about "Delay compensation" patented technology

Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

The present disclosure provides a pulse trigger and a phase discriminator. The pulse trigger includes a logic module, a first input stage module, and a second input stage module; the circuit structures of the first input stage module and the second input stage module are the same; the logic module includes a first charging path corresponding to the positive terminal signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive terminal signal of the differential signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; the logic module is respectively connected to the first input stage module and the second input stage module. When the first clock signal is a rising edge signal, the logic module conducts based on the input signals of the first input stage module and the second input stage module, and the inverted output terminal of the pulse trigger outputs a high-level signal. By accelerating the charge and discharge stages of the pulse trigger, shortening the dead time, and improving the resolution of the pulse trigger, static errors are eliminated.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

The invention provides an ultra-high-speed level conversion circuit of a digital circuit, and relates to the technical field of level conversion of DC-DC application, and the ultra-high-speed level conversion circuit comprises a DC-DC high-side driving module which is used for ultra-high-speed level conversion and comprises a high-level converter. A low-voltage input signal hsinlv drives cfly1 and cfly2 through inverters inv1 and inv2, so that driving delay below 50pS can be easily realized, transmission delay after cfly1 and cfly2 bootstrap can be ignored, the driving delay from inhv and inphv to output hsinhv is driving delay of a logic gate and can be easily below 50pS, delay from the low-voltage input signal hsinlv to a high-voltage output signal hsinhv is transmission delay between digital gates, and the transmission delay between the digital gates is greatly reduced. And the transmission delay below 100pS can be easily realized.

Embodiments provide a power supply switching circuit, which generates a first control signal jointly by utilizing a first input signal and a first drive signal opposite in phase to a second control signal, and generates the second control signal jointly by utilizing a second input signal and a second drive signal opposite in phase to the first control signal, such that time (i.e., overlap time) required for simultaneously turning on or off a first output subcircuit and a second output subcircuit is greatly reduced or even eliminated, effective output of an output node is implemented, and reliability of a device is improved. Furthermore, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power supply switching circuit is simple and reliable in control logic and is insensitive to process, which further improves the reliability of the device.

The invention discloses a time delay circuit, which comprises a time delay module used for carrying out transmission time delay on input logic data, the time delay module comprises at least two time delay units which are connected in series, each time delay unit comprises a phase inverter and a capacitor, the input end of the phase inverter receives an input signal of the time delay unit, and the output end of the phase inverter receives an output signal of the time delay unit. The output end of the phase inverter provides an output signal of the time delay unit, the first end of each capacitor is connected with the output end of the phase inverter, the second end of each capacitor receives control voltage, and the control voltage generation module is used for adjusting the control voltage provided for each capacitor according to the value of the input logic data so as to control the time delay unit. According to the time delay circuit, the capacitance value of each capacitor is adjusted, so that the time delay circuit can perform different transmission delays on different logic data, and a time difference with a determined proportion is formed between the two kinds of logic data, so that specific synchronous or asynchronous requirements are met.

The embodiment of the invention provides a delay compensation method for a configurable peripheral input and output pin and a related product. The method comprises the steps that an input and output delay adjustment circuit detects whether a delay compensation requirement for the configurable peripheral input and output pin exists or not currently; and when the configurable peripheral input / output pin has a delay compensation requirement, the input / output delay adjustment circuit adjusts the delay of the configurable peripheral input / output pin. According to the embodiment of the invention, the delay of the input and output pins of the configurable peripheral can be adjusted through the input and output delay adjusting circuit, so that the flexibility of wiring design of a user circuit board can be ensured, and the reliability of data communication with the high-speed peripheral can be improved.

The application discloses a low-latency driving circuit and a driving device. The low-latency driving circuit comprises an output transistor, an output terminal of which is connected to or serves as a driving output terminal of the driving circuit; and a first control transistor, an input terminal of which is connected to a first voltage level, and an output terminal of which is connected to a control terminal of the output transistor; wherein when the driving circuit switches to an open output, the first control transistor is turned on and the first voltage level is applied to the control terminal of the output transistor to raise the voltage of the driving output terminal. The low-latency driving circuit provided by the application can reduce the delay of output response under the premise of providing adjustable driving circuit output, so as to adapt to high-precision and fast-response application scenarios.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

A CAN bus transmitter has inputs for receiving transmitted data signals, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter includes multiple CAN driver circuits with inputs coupled to their common CANH and CANL outputs and connected to the CAN bus via delay circuits. Matching of the Cgs capacitors between devices in the CANH and CANL branches provides substantially synchronized changes in the CANH and CANL output logic levels as the input logic levels change. The variable delay of this input logic level change for each of the multiple CAN driver circuits reduces the transmission of unwanted signals from the CAN bus.

The invention discloses an input and output circuit, which comprises an input and output module, a high selection module, a control module and a protection switch module, and is characterized in that the input and output module comprises a pull-up PMOS (P-channel Metal Oxide Semiconductor) tube and a logic driving module. The high selection module compares the PAD end voltage with the power supply voltage and outputs the higher voltage as the substrate control signal end voltage, so as to ensure that the substrate voltage of the pull-up PMOS tube is not lower than the PAD end voltage; meanwhile, a transmission gate switch structure in the related technology is replaced by a structure that an inverter is connected with a PMOS in series, a control module generates a protection control signal based on the working state of a power supply voltage end, and a logic protection unit and a driving protection unit in a protection switch module are used for respectively controlling a current path of a logic unit and the working state of a pull-up PMOS tube. Therefore, the current backflow phenomenon is prevented, and the chip and connection equipment are protected.

The invention discloses a turn-on time control circuit, a circuit board and electronic equipment, and belongs to the field of electronic circuits, and the turn-on time control circuit comprises a conversion module, a current mirror module, a generation module and a control module. The conversion module outputs a related first current according to an external load input voltage, and the current mirroring module mirrors the first current to generate a second current. The generation module comprises a charging unit and a charging control unit, the charging unit receives the second current for charging, and the charging control unit controls the charging process according to the voltage at the two ends of the charging unit and the external load output voltage and ensures that the charging voltage is not zero. The control module adjusts the charging time of the charging unit through the external output reference voltage and the output voltage so as to control the conduction time of the current mirror image module, the undershoot voltage of the output voltage when the load transients can be reduced, and the stability of the power supply in a high-load state is improved.

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.

The invention provides an asynchronous subthreshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting at least one basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the series connection number of a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit does not exceed a preset series connection number upper limit; a sensitive amplifier-transmission transistor logic circuit directly connected with the input end of the trigger unit is determined from the first sub-threshold logic circuit; replacing the sense amplifier-pass transistor logic circuit with an asynchronous detection sense amplifier-pass transistor logic circuit; and deleting the clock circuit in the first sub-threshold logic circuit to form a second sub-threshold logic circuit. Signal weakening is reduced, time delay is reduced, the working frequency of the sub-threshold logic circuit is improved, and a transmission transistor network is adopted to support circuit units with unfixed logic functions.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven. The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

The invention discloses a frequency-voltage conversion circuit, which realizes the function of generating a two-phase switch control signal with a phase difference by multiplexing a clock input signal representing frequency information in front of a frequency dividing circuit and performing simple combinational logic on the clock input signal and a frequency dividing signal. Therefore, the influence of process, voltage or temperature fluctuation on the stability of the circuit is avoided.

The invention relates to the technical field of latches, and discloses a high-performance low-overhead four-point reinforced latch based on dual modular redundancy, which comprises an input module, a storage module L1 and a storage module L2, the storage module L1 and the storage module L2 are connected with the input module, and the storage module L1 and the storage module L2 are connected with an output module; and the input module comprises a transmission gate TG1-a transmission gate TG10 which are connected with the storage module L1 and the storage module L2. According to the method, internal four-node overturning can be completely tolerated, and meanwhile, the method has a relatively high four-node overturning self-recovery rate and relatively high reinforcing performance and reliability; a double-input C unit stacking structure is adopted, the leakage power consumption is greatly reduced, and the clock control double-input C unit is utilized, so that the dynamic power consumption is reduced; only one transmission gate is arranged from the input end to the output end in a transparent mode, so that the latch has low time delay and can be widely applied to the fields of aerospace and the like with high requirements on reliability and low power consumption of the latch.

An integrated circuit (IC) device includes first and second dies. The first die includes a first transmit circuit, a first receive circuit, and a first circuit. The first transmission circuit transmits an output clock signal corresponding to the first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs a first signal corresponding to the input signal based on the input clock signal. The first circuit outputs a second signal corresponding to the first signal based on the first clock signal. The second die includes a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal, and a second transmitting circuit coupled to the first receiving circuit and transmitting an input signal and an input clock signal corresponding to the output clock signal to the first receiving circuit based on the output clock signal. The embodiment of the invention also discloses a method for operating the integrated circuit device.

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

The present invention relates to the field of integrated circuit technology, and specifically to a high-voltage level shift circuit suitable for a GaN driver chip. The circuit converts a signal in a low-voltage domain into a signal in a high-voltage domain, and is characterized in that it includes a voltage-to-current signal module, a current mirror module, a push-pull output module, a current compensation branch, and a signal maintenance module; the voltage-to-current signal module is used to convert a PWM voltage signal into a current signal, the current mirror module is used to mirror the current signal converted by the PWM voltage as the input signal of the push-pull output module, the push-pull output module converts the current signal into a voltage signal in the high-voltage domain, the current compensation branch is used to compensate for the current of the node, and the signal maintenance module provides a small current to maintain the established signal state. This solution effectively solves the contradiction between power consumption, transmission delay, CMTI capability, and the ability to resist negative pressure of the switch node in the traditional level shift circuit.

This application provides a level shifter and a high-voltage half-bridge driver, belonging to the field of high-voltage power integrated circuit technology. The level shifter includes a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module. The first capacitor driving module generates a first pulse signal; the first pulse sensing module generates a fourth pulse signal; the second pulse sensing module generates a seventh pulse signal; the latch output module generates a target pulse signal and sends a feedback signal when the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. This application can reduce the signal transmission delay and power consumption of the level shifter and improve reliability.

The embodiment of the invention relates to a preset control loop for a PPG LED driver. According to an embodiment, a driver circuit for a light emitter in a photoplethysmography (PPG) system includes a main control loop having an operational amplifier and a transistor configured as a source follower. During the preset control stage, the preset circuit sets the output voltage of the operational amplifier to be a preset level. The switching circuit activates the preset circuit in a preset phase and activates the main control loop in a main control phase. Before the main control loop is activated, the preset circuit pre-regulates the gate voltage of the source follower transistor to be close to its threshold voltage. This improves startup performance by reducing delay and uncontrolled initial current while avoiding the need for amplifier trimming. The circuit can realize fast stabilization time and accurate control of short current pulse at a very low duty ratio, and is beneficial to PPG measurement accuracy and power efficiency in wearable health care monitoring equipment.

The invention discloses a low-jitter clock fan-out buffer with frequency division and delay adjustment. A clock input buffer module is used for buffering single-ended or differential clock frequency; the clock fan-out module is used for fan-out of the clock signal generated by the clock input buffer module to four frequency division amp; a time delay module; frequency division amp is carried out; the delay module is used for carrying out frequency division on the signal of the clock input buffer module to a required output signal and carrying out delay adjustment; the output driver module divides the frequency into amp; an output signal generated by the delay module is converted into one of three output formats of HSTL, LVDS and LVCMOS to drive an output load; the reference module is used for providing reference current for the clock input buffer module and the clock fan-out module. The multi-mode fan-out clock circuit has the functions of adjustable fan-out frequency and delay, low output jitter and multi-mode signal output, and can achieve excellent fan-out clock precision in a wide frequency range. And the method has excellent jitter performance and is suitable for fan-out buffer application of infrastructure clocks with strict requirements.

A multi-channel digital isolator includes a digital isolator and an interlock circuit. The isolator includes a transmitter having a transmitter output, a receiver having a receiver input and a receiver output, an isolation barrier coupled between the transmitter output and the receiver input, and an output buffer having a buffer input and configured to output an isolated signal. The transmitter is configured to transmit an input signal across the isolation barrier. The interlock circuit has an interlock input coupled to the receiver output and an interlock output coupled to the buffer input. The interlock module is configured to prevent overlapping active states between the first isolated signal and a complementary isolated signal. In some implementations, the digital isolator also includes a dead-time insertion circuit.

The embodiment of the invention provides a clock duty ratio correction circuit and a serializer / deserializer. The clock duty ratio correction circuit comprises a time delay module and an edge capture module, the time delay module comprises a plurality of controllable capacitors and is used for controlling the time delay of input clock signals by controlling the number of the controllable capacitors connected into a circuit and outputting two paths of time delay clock signals; the edge capturing module comprises four field effect transistors and is used for receiving the two paths of delay clock signals and performing edge selection on the two paths of delay clock signals through one path of control signal; an output clock signal is determined according to the edge selection result, and the duty ratio of the output clock signal is determined by the delay size of the two delay clock signals. According to the embodiment of the invention, the problem that a clock duty ratio correction circuit with higher calibration precision, lower power consumption and smaller integrated area is needed along with the increase of the communication rate in the prior art is solved.

The present disclosure relates to a semiconductor device and an electronic control device. A semiconductor device and an electronic control device capable of cutting off a reverse current from a load to a power supply are provided. A power transistor QN1 is provided between a positive power supply terminal Pi2(+) and a load driving terminal Po2(+), and has a source and a back gate coupled to the positive power supply terminal Pi2(+). A power transistor QN2 is provided in series with the power transistor QN1, and a source and a back gate of the power transistor QN2 are coupled to the load driving terminal Po2(+). A booster CP1a charges the gate of the power transistor QN1. When the potential of the negative power supply terminal Pi2(−) is higher than the potential of the positive power supply terminal Pi2(+), a gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source.

The invention provides a signal conversion circuit capable of changing unipolar control into bipolar control. The signal conversion circuit comprises a time delay circuit and a level conversion circuit, the delay circuit comprises a capacitor and a first resistor which are connected in parallel, one ends of the capacitor and the first resistor are electrically connected to the first signal line, and the other ends are grounded; the level conversion circuit comprises a triode, the base electrode of the triode is electrically connected with a second signal line, the collector electrode of the triode is electrically connected with one end of a second resistor, the other end of the second resistor is electrically connected with the positive electrode of the control electrode, the emitter electrode of the triode is electrically connected with one end of a third resistor, and the other end of the third resistor is grounded. The collector electrode of the triode is electrically connected with an output signal line. Synchronization of bipolar control signals is achieved through the time delay circuit, and the situation that the circuit cannot work normally due to the fact that bipolar signals are not synchronous is avoided. And level conversion is realized through switching on and switching off of the triodes, single-pole control is changed into double-pole control, and the stability of control signals is effectively improved.

An input / output (I / O) sensor for a multi-IC module. The I / O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An integrated circuit (IC) device includes a first die including a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The first circuit, in response to a first value of a first selection signal, outputs the second signal in response to a first edge of the first clock signal. The first circuit, in response to a second value different from the first value of the first selection signal, outputs the second signal in response to a second edge of the first clock signal.