4results about "Delay compensation" patented technology

This invention describes an integrated circuit and a method for designing an integrated circuit including error detection and correction circuitry. The integrated circuit includes a data path arranged between the output of a first register timed by a system clock and a second register. The integrated circuit includes timing error detection and correction circuitry (EDAC) having a clock unit configured to receive a reference clock and provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to corresponding nodes on the data path and error detection circuitry coupled to each transition detector. During design, the nodes are selected according to a desired timing window to be monitored. If a transition occurs during a snapshot of a time period between a transition corresponding to the reference clock and a corresponding transition of the delayed reference clock, the error detection circuitry flags an error. The timing correction circuitry coupled to the error detection circuitry outputs the system clock derived from the delayed reference clock.

An input / output (I / O) sensor for a multi-IC module. The I / O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

An apparatus comprises a first OR gate, a second OR gate, a first NAND gate, and a second NAND gate. The first OR gate comprises a first input terminal, a second input terminal, and an output terminal. The second OR gate comprises a first input terminal, a second input terminal, and an output terminal. The first NAND gate comprises a first input terminal coupled to the output terminal of the first OR gate. The first NAND gate also comprises a second input terminal coupled to the output terminal of the second OR gate. The second NAND gate comprises an output terminal coupled to the first input terminal of the second OR gate.