11 results about "Positive logic" patented technology

The utility model discloses a 0-10V dimming control circuit, a dimming power supply and a dimming controller. According to the 0-10V dimming control circuit, when negative logic dimming is carried out and the voltage of a connecting port of a dimmer reaches the maximum, an MCU unit controls a switching device to be switched off so as to disconnect a pull-up resistor and a direct-current power supply, and meanwhile, the MCU unit outputs an excitation voltage to the input end of a voltage follower; the MCU unit judges whether the dimmer connection port is connected with the dimmer according to the magnitude change of the voltage detection signal output by the voltage follower, and further distinguishes whether the maximum voltage of the dimmer connection port is caused by the maximum output of the dimmer or the suspension of the dimmer connection port; the 0-10V dimming control circuit solves the technical problem that a conventional positive logic 0-10V dimming control circuit cannot be compatible with negative logic dimming, can be compatible with positive and negative logic dimming at the same time, is compatible with an active dimmer and a passive dimmer, and is higher in universality.

This invention discloses a design method and apparatus for a general-purpose aging board for DIP-like packaged module circuits, belonging to the field of power module circuit aging testing. By fully utilizing the commonalities of DIP-like packaged module circuits, this invention creates more versatile fixtures, improving fixture compatibility and achieving full coverage of DIP-like package pin spans within 50.8mm. This reduces the design time and procurement costs of custom-made fixtures, improving design efficiency. Under different power conditions, crown spring holes are used as resistor connectors, enabling free insertion and replacement between different load resistors, reducing the cost of repeatedly customizing fixtures and manufacturing boards due to different load resistors, and improving efficiency. When only the connection method of the CTRL pin differs—negative logic requires grounding, positive logic requires floating—the design of pin headers and jumpers allows for flexible connection selection, reducing overall hardware manufacturing costs. This invention is suitable for large-scale design and storage, and offers high testing efficiency.

An artificial intelligence system may include a language center, a logic processing unit, and an evolution code generator. In one embodiment, the logic processing unit may include a symbolic processing unit, a combinational logic, and a sequential logic state machine. A natural language query can be transmitted to the symbolic processing unit from the language center to produce symbolic logic expressions, and then transmitted to the combinational logic and the sequential logic state machine to produce optimized symbolic outputs and validated state transitions, which can be sent to the evolution code generator for further optimization. This further optimized language can be transmitted back to the combinational logic to correct logic contradictory, and / or to the sequential logic state machine to trigger for a state transition in the event sequence.

It is possible to monitor the error detection and correction (EDAC) logic of a memory subsystem for error correction, where the EDAC logic is configured to use a first EDAC level. It is possible to determine the number of error corrections performed by the EDAC logic when using the first EDAC level during a time interval. When the number of error corrections using the first EDAC level during the time interval exceeds a threshold, the EDAC logic can switch from using the first EDAC level to using a second EDAC level.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The present invention relates to the field of level conversion drivers for phased array circuits and systems, specifically a temperature-compensated level conversion driver, comprising: a logic level positive-to-negative conversion unit and a drive shaping unit connected thereto; the logic level positive-to-negative conversion unit comprising a feedback-enhanced transistor voltage drop unit formed by connecting P Schottky diodes in series with transistors, an enhancement-type transistor voltage drop unit formed by short-circuiting the drain and gate of M transistors, and positive temperature coefficient resistors RB1 and RB2. By introducing the feedback-enhanced transistor voltage drop unit formed by connecting P Schottky diodes in series with transistors, the enhancement-type transistor voltage drop unit formed by short-circuiting the drain and gate of M transistors, and the positive temperature coefficient resistors RB1 and RB2, temperature compensation is achieved while converting a positive logic level to a negative logic level. The present invention improves the temperature sensitivity of the flip level and is applicable to complex working environments with anti-interference requirements.

The invention relates to cross-use of positive and negative logic adders. According to an exemplary embodiment, the present disclosure discloses a multi-bit adder, which may include: a negative logic adder circuit; wherein an input signal of the negative logic adder circuit comprises at least one negative logic signal, and an output signal of the negative logic adder circuit comprises at least one positive logic signal. The technical scheme disclosed by the invention has the effects of reducing the use quantity of the transistors, reducing the power consumption and the area of the multi-bit adder and improving the operation speed of the multi-bit adder circuit at the same time.

The invention relates to the field of level conversion drivers applied to phased array circuits and systems, in particular to a temperature compensation level conversion driver which comprises a logic level positive-to-negative unit and a driving shaping unit connected with the logic level positive-to-negative unit. The logic level positive-to-negative unit comprises a feedback enhanced transistor voltage drop unit formed by connecting P Schottky diodes and transistors in series, an enhanced transistor voltage drop unit formed by short-circuiting drain electrodes and grid electrodes of M transistors, and positive temperature coefficient resistors RB1 and RB2; through introduction of a feedback enhanced transistor voltage drop unit formed by series connection of P Schottky diodes and transistors, an enhanced transistor voltage drop unit formed by short circuit of drain electrodes and grid electrodes of M transistors, and positive temperature coefficient resistors RB1 and RB2, temperature compensation is realized while conversion from a positive logic level to a negative logic level is realized. According to the invention, the temperature sensitivity of the flip level is improved, and the flip level can be applied to a complex working environment with an anti-interference requirement.

The application provides a reverse logic method and device of configuration interlocking logic, a storage medium and an electronic device, and the method is: obtaining an interlocking logic diagram corresponding to a positive logic of an automatic control system; identifying a logic paragraph in the interlocking logic diagram; determining a target logic paragraph in the logic paragraph, the target logic paragraph being a logic paragraph containing an output bit number; establishing a logic node tree corresponding to the target logic paragraph; and performing reverse logic according to a level of the logic node tree to obtain an anti-logic interlocking configuration corresponding to the target logic paragraph. In the scheme, the logic paragraph is identified from the interlocking logic diagram, and the target logic paragraph in the logic paragraph is determined. The logic node tree corresponding to the target logic paragraph is established, the reverse logic is performed according to the level of the logic node tree, and the anti-logic interlocking configuration corresponding to the target logic paragraph is obtained. The anti-logic does not need to be manually drawn, and the configuration cost is reduced and the configuration efficiency is improved.

The utility model provides a short-circuit overcurrent fault self-locking protection circuit, and belongs to the technical field of circuit protection, the short-circuit overcurrent fault self-locking protection circuit specifically comprises a current sensor, an operational amplifier, a positive logic optocoupler relay, an MOS tube, a diode, a capacitor and a resistor, a VCC pin of the current sensor is connected with an auxiliary source, and a VOUT pin is sequentially connected with a first resistor and a second resistor; the input positive end of the operational amplifier is connected between the first resistor and the second resistor, the VREF pin of the current sensor is connected with the input negative end of the operational amplifier, the capacitor is connected in parallel to the two ends of the second resistor, and the output end of the operational amplifier is fed back to the input positive end of the operational amplifier through the third resistor and the diode which are sequentially connected in series. The output end of the operational amplifier is further connected with the input end of the positive logic optocoupler relay, the MOS tube is connected to the negative end of the loop in series, and the output end of the positive logic optocoupler relay is connected with the MOS tube. According to the circuit, the reflection time and the overcurrent point can be flexibly set, and the reliability and the stability of a product are improved.

The utility model relates to the technical field of circuit design, in particular to a circuit compatible with positive logic and negative logic control, which comprises an operational amplifier, a target diode, a power input end and an ON / OFF end, the target diode is arranged between the first pin of the operational amplifier and the ON / OFF end, or the target diode is arranged between the third pin of the operational amplifier and the ON / OFF end; when the target diode is arranged between the first pin position and the ON / OFF end of the operational amplifier, the conduction end of the target diode is also connected with the power supply input end; and when the target diode is arranged between the third pin of the operational amplifier and the ON / OFF end, the ON / OFF end is also connected with the power supply input end. The positive logic control mode and the negative logic control mode can be compatible on the same PCB, redesign and remanufacturing are not needed, design flexibility is improved, meanwhile, repeated PCB design and production are avoided, and therefore manufacturing cost is reduced.