4 results about "Positive logic" patented technology

This invention discloses a design method and apparatus for a general-purpose aging board for DIP-like packaged module circuits, belonging to the field of power module circuit aging testing. By fully utilizing the commonalities of DIP-like packaged module circuits, this invention creates more versatile fixtures, improving fixture compatibility and achieving full coverage of DIP-like package pin spans within 50.8mm. This reduces the design time and procurement costs of custom-made fixtures, improving design efficiency. Under different power conditions, crown spring holes are used as resistor connectors, enabling free insertion and replacement between different load resistors, reducing the cost of repeatedly customizing fixtures and manufacturing boards due to different load resistors, and improving efficiency. When only the connection method of the CTRL pin differs—negative logic requires grounding, positive logic requires floating—the design of pin headers and jumpers allows for flexible connection selection, reducing overall hardware manufacturing costs. This invention is suitable for large-scale design and storage, and offers high testing efficiency.

An artificial intelligence system may include a language center, a logic processing unit, and an evolution code generator. In one embodiment, the logic processing unit may include a symbolic processing unit, a combinational logic, and a sequential logic state machine. A natural language query can be transmitted to the symbolic processing unit from the language center to produce symbolic logic expressions, and then transmitted to the combinational logic and the sequential logic state machine to produce optimized symbolic outputs and validated state transitions, which can be sent to the evolution code generator for further optimization. This further optimized language can be transmitted back to the combinational logic to correct logic contradictory, and / or to the sequential logic state machine to trigger for a state transition in the event sequence.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion / mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The invention relates to cross-use of positive and negative logic adders. According to an exemplary embodiment, the present disclosure discloses a multi-bit adder, which may include: a negative logic adder circuit; wherein an input signal of the negative logic adder circuit comprises at least one negative logic signal, and an output signal of the negative logic adder circuit comprises at least one positive logic signal. The technical scheme disclosed by the invention has the effects of reducing the use quantity of the transistors, reducing the power consumption and the area of the multi-bit adder and improving the operation speed of the multi-bit adder circuit at the same time.