Successive approximation type analog-to-digital converter with capacitance mismatch correction function

A successive approximation, analog-to-digital converter technology, applied in the direction of analog/digital conversion, analog/digital conversion calibration/test, code conversion, etc., can solve the problem of high hardware overhead of digital circuits, increased circuit area and power consumption, and algorithm Convergence and other issues, to simplify the design process, reduce area and complexity, simple and reliable digital circuit

Active Publication Date: 2020-07-17
成都铭科思微电子技术有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Using a non-binary capacitor array can eliminate the dynamic error caused by incomplete DAC establishment or reference voltage jitter during the quantization process, but the value of each capacitor is no longer equal to the sum of all its low-level capacitors, making the above-mentioned foreground self-calibration no longer applicable
In addition, the use of auxiliary DAC increases the circuit area and power consumption
[0012] For background self-calibration, it involves the convergence of the algorith

Method used

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  • Successive approximation type analog-to-digital converter with capacitance mismatch correction function
  • Successive approximation type analog-to-digital converter with capacitance mismatch correction function
  • Successive approximation type analog-to-digital converter with capacitance mismatch correction function

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Embodiment 1

[0053] The present invention designs a successive approximation analog-to-digital converter with capacitance mismatch correction function, such as Figure 1~3 As shown, the following setting method is adopted in particular: a P-terminal DAC102, an N-terminal DAC104, a comparator 106, a SAR logic circuit 108, a correction logic circuit 110 and a correction control circuit 112 are provided, and the output terminal of the P-terminal DAC102 and the N-terminal The output end of DAC104 connects two input ends of comparator 106 respectively, and the output connection of comparator 106 connects SAR logic circuit 108, and SAR logic circuit 108 controls and connects P end DAC102, N end DAC104 and correction logic circuit 110, correction control circuit 112 The control is connected to the SAR logic circuit 108 and the correction logic circuit 110 ; the analog input signal is input on the P-terminal DAC102 , and the signal ground is connected to the N-terminal DAC104 .

[0054] As a prefe...

Embodiment 2

[0056] This embodiment is further optimized on the basis of the above embodiments, such as Figure 1~3 As shown, the same parts as the aforementioned technical solutions will not be repeated here. Further, in order to better realize the present invention, the following setting method is adopted in particular: the P-terminal DAC102 and the N-terminal DAC104 adopt the same DAC circuit structure, And the DAC circuit structure includes a high segment capacitor array 202, a low segment capacitor array 204, a fractional capacitor array 206 and a C C correction capacitor array 208, the C C The correction capacitor array 208 is connected to the fractional capacitor array 206, and the fractional capacitor array 206 is connected to the low segment capacitor array 204, and the capacitor C is passed between the high segment capacitor array 202 and the low segment capacitor array 204. C Coupling; at least one binary capacitor array is set in the high segment capacitor array 202 and the lo...

Embodiment 3

[0059] This embodiment is further optimized on the basis of any of the above embodiments, such as image 3 As shown, the same part as the foregoing technical solution will not be repeated here. In this embodiment, a binary 14-bit DAC (P-terminal DAC 102 or N-terminal DAC 104) with a redundant structure is used as an example as an example. The DAC structure By the high segment capacitor array 202, the low segment capacitor array 204, the decimal capacitor array 206 and C C The correction capacitor array 208 is composed of a capacitor C between the high segment capacitor array 202 and the low segment capacitor array 204 C for coupling. The high-segment capacitor array 202 is composed of 11 capacitors, which are respectively C 1 ~C 5 、C 5R 、C 6 ~C 9 and C 9R . where C 1 is the highest capacitance of the high-segment capacitance array 202, and is also the MSB capacitance of the entire SAR_ADC, C 9 is the lowest bit capacitance of the high-segment capacitance array 202, C...

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Abstract

The invention discloses a successive approximation type analog-to-digital converter with a capacitor mismatch correction function. The circuit is provided with a P-end DAC (102), an N-end DAC (104), acomparator (106), an SAR logic circuit (108), a correction logic circuit (110) and a correction control circuit (112). The output end of the P-end DAC (102) and the output end of the N-end DAC (104)are respectively connected with two input ends of the comparator (106). Wherein the output of the comparator (106) is connected with the SAR logic circuit (108); the SAR logic circuit (108) is in control connection with the P-end DAC (102), the N-end DAC (104) and the correction logic circuit (110); and the correction control circuit (112) is in control connection with the SAR logic circuit (108)and the correction logic circuit (110).

Description

technical field [0001] The invention relates to the field of analog integrated circuit technology and the like, specifically, a successive approximation analog-to-digital converter with capacitance mismatch correction function. Background technique [0002] SAR_ADC (Successive Approximation Analog-to-Digital Converter) is a common architecture of ADC (Analog-to-Digital Converter). The charge redistribution SAR_ADC using capacitor array has become the mainstream structure of SAR_ADC due to good capacitor matching and low static power consumption. Usually, an N-bit SAR_ADC contains an N-bit binary capacitor array, namely 1C, 2C, 4C, ..., 2N-1C, where C is the unit capacitance, 2N-1C corresponds to the MSB (highest bit), and 1C corresponds to the LSB (lowest bits). [0003] For high-resolution SAR_ADC, such as N=14 or 16, the binary capacitor array will occupy a large chip area, and the maximum capacitance and minimum capacitance are very different, making it difficult to ach...

Claims

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Application Information

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IPC IPC(8): H03M1/10
CPCH03M1/1033H03M1/1014Y02D30/70
Inventor 杜翎李昌红吴霜毅
Owner 成都铭科思微电子技术有限责任公司
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