Optimization method and device for sub-threshold circuit design

Abstract

The invention provides an optimization method and device for a sub-threshold circuit design.. Query data of a logic unit under different threshold voltages are preset, and the query data comprise device parameters-delay data; delay analysis is carried out on a to-be-optimized sub-threshold circuit; for a to-be-optimized path with unmatched delay, device parameters of a logic unit in a path are adjusted to perform deplay optimization; adjusted device parameters are determined through preset query data during optimization, meanwhile, the device parameters of each logic unit in the delay circuitto be optimized are changed by adopting different threshold voltages, and finally, tthe unit device parameters corresponding to each logic unit in the delay circuit to be optimized under the condition of minimum power consumption are taken as an optimization result. Therefore, power consumption is reduced while delay optimization is carried out.

Description

technical field [0001] The invention relates to the field of automatic design of integrated circuits, in particular to an optimization method and device for sub-threshold circuit design. Background technique [0002] A subthreshold circuit refers to a circuit whose operating voltage is lower than the threshold voltage of a transistor device. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. [0003] In the design process of sub-threshold digital circuits (hereinafter referred to as sub-threshold circuits), delay optimization is one of the key and difficult points. At present, in the delay optimization of sub-threshold circuits, the method of adjusting the gate width / gate length ratio is mainly adopted according to the delay signal size, and the gate is increased for devices on the path where the delay signal is large and the delay needs to be reduced. The ratio of gate wid...

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Problems solved by technology

At present, in the delay optimization of sub-threshold circuits, the method of adjusting the gate width / gate length ratio is mainly adopted according to the delay signal size, and the gate is increased for devices on the path where the delay signal is large and the delay needs to be reduced. The ratio of gate width / gate length is reduced, and the ratio of gate width / gate length is reduced for devices on the path where the delay signal is small and needs to be increased. However, increasing the ratio of gate width / gate length reduces delay, but it will Increased device unit area and power consumption

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