5results about "Data rate detection arrangements" patented technology

An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

A circuit can enable communication between a primary device and one or more secondary devices. This communication can use a Universal Asynchronous Receiver Transmitter (UART) protocol. During operation, the primary device may require information about the baud rate of the secondary device. The UART can operate in reverse polarity mode, and this reverse polarity can be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using reverse polarity mode to enter auto-baud detection mode can prevent excessive delays in UART communication and avoid the need for additional pins to implement the auto-baud detection mode.

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate pre-encoded data, and a transmitter configured to transmit the pre-encoded data through a transmission channel, and a second device including an integrator configured to perform integration on the pre-encoded data, integration samplers including a plurality of samplers configured to output sampled data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the pre-encoded data and a clock based on the decoded data and an output of another one of the samplers.

Disclosed is a platform-agnostic 5G Distributed Unit (DU) Physical Layer (PHY) application deployable on general-purpose processors (GPPs) across multiple CPU architectures. The disclosed system decouples DU software from specific hardware platforms by utilizing SIMD abstraction and substitution libraries that enable portable vectorized signal processing. The PHY application may be deployed on both x86-based and Arm-based processors from a single source codebase. In-memory signal processing techniques minimize latency by managing data through pointers and performing operations in registers. The architecture supports containerized deployment and enables operators to select hardware components tailored to their requirements while maintaining functional equivalence across platforms. The disclosed approach may provide energy efficiency benefits through flexible processor selection.

Disclosed is a platform-agnostic 5G Distributed Unit (DU) Physical Layer (PHY) application deployable on general -purpose processors (GPPs) across multiple CPU architectures. The disclosed system decouples DU software from specific hardware platforms by utilizing SDMD abstraction and substitution libraries that enable portable vectorized signal processing. The PHY application may be deployed on both x86-based and Arm-based processors from a single source codebase. In-memory signal processing techniques minimize latency by managing data through pointers and performing operations in registers. The architecture supports containerized deployment and enables operators to select hardware components tailored to their requirements while maintaining functional equivalence across platforms. The disclosed approach may provide energy efficiency benefits through flexible processor selection.