28results about "Data rate detection arrangements" patented technology

This application provides a method and an apparatus for adjusting a transmission rate, a processor, a network device, and a system. The method includes: obtaining first data at a first rate; adding additional data to the first data in a specific proportion to obtain second data; and sending the second data at a second rate, where the second rate is greater than the first rate. A transmission rate is increased by adding the additional data to the first data in the specific proportion, to break a limitation of a backplane on device capacity expansion and upgrade during device capacity expansion and upgrade. This can not only avoid a frequency hole, but also can meet a future performance requirement.

A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.

The invention provides an MLSE balanced receiving method and device, and the method comprises the steps: receiving a to-be-recovered signal formed by a signal transmitted at each moment, and enabling the to-be-recovered signal to be obtained through the channel transmission and noise addition of a transmitted signal; for each moment, comparing the state metrics for transferring each possible signal state at the previous moment to the signal state at the current moment, and determining a target state transfer path for transferring the signal state at the previous moment to the signal state at the current moment when the state metric is maximum, determining the signal state at the previous moment when the state measurement is maximum as the maximum possible signal state at the previous moment; and determining an equalization signal corresponding to the to-be-recovered signal based on the target state transition path at each moment and a signal state corresponding to a maximum state metric in the state metrics of each possible signal state at the last moment and each possible signal state at the last moment of each moment. According to the invention, the equalization complexity can be reduced.

A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.

An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

A wireless networking system is provided. The wireless networking system includes a base station device including processing circuitry configured to detect a transmission rate from a portion of a preamble of an incoming packet transmission signal and adapt a radio configuration to receive a remainder of the incoming packet transmission signal at the transmission rate.

Techniques that provide link auto-negotiation between a radio equipment controller (REC) and a radio equipment (RE) are described herein. In one embodiment, a method includes performing, by a proxy master, a Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation with a RE to achieve a L1 synchronization between the proxy master and the RE at a link bit rate; communicating the link bit rate from the proxy master to a proxy slave; performing, by the proxy slave, a CPRI L1 link auto-negotiation with a REC to determine whether a L1 synchronization between the proxy slave and the REC is achieved, wherein if the L1 synchronization is achieved, the link bit rate is a common matching link bit rate achieved; and upon the common matching link bit rate being achieved, establishing a CPRI link between the REC and the RE using the common matching link bit rate.

The application relates to the technical field of communication, in particular to a data receiving method, a data sending method and a computer readable storage medium. The method comprises the following steps: when a fault signal is detected, a fault starting signal is sent, and a first time when the fault starting signal is sent is recorded, the fault starting signal is used for acquiring a plurality of groups of fault data packets, and the sampling frequency of the plurality of groups of fault data packets is a preset sampling frequency; a first fault data packet is received, and a second time when the first fault data packet is received is recorded, the first fault data packet is a first group of fault data packets in the plurality of groups of fault data packets; a plurality of sampling time marks of the plurality of groups of fault data packets are calculated according to the preset sampling frequency, the first time and the second time, the preset sampling frequency and the frequency required by a fault detection waveform of a data receiving end are matched, high-frequency sampling data transmission can be realized, the required data transmission flow is saved, the accuracy of fault analysis is improved, and digital sampling is realized.

A circuit can enable communication between a primary device and one or more secondary devices. This communication can use a Universal Asynchronous Receiver Transmitter (UART) protocol. During operation, the primary device may require information about the baud rate of the secondary device. The UART can operate in reverse polarity mode, and this reverse polarity can be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using reverse polarity mode to enter auto-baud detection mode can prevent excessive delays in UART communication and avoid the need for additional pins to implement the auto-baud detection mode.

This application provides a method, apparatus, processor, network device, and system for improving transmission rate. The method includes: obtaining first data at a first rate; adding additional data to the first data at a certain proportion to obtain second data; and transmitting the second data at a second rate greater than the first rate. By adding additional data to the first data at a certain proportion, the transmission rate is increased, thereby breaking the limitations imposed by the backplane on device expansion and upgrades. This not only avoids frequency gaps but also adapts to future performance requirements.

A serial data receiver subsystem included in a computer system may include a data detection circuit, a speed detection circuit, and a receiver circuit that includes multiple subcircuits. The data detection circuit performs a comparison a reference voltage to the magnitude of signals received via a communication link that encode a serial data stream consisting of multiple data symbols. Using a result of the comparison, the data detection circuit may activate a indicating the presence of data on the communication link. Once the is active, the speed detection circuit checks the number of transitions to determine a rate at which data is being transmitted. In response to a determination that the rate of the data being transmitted exceeds a threshold value, the receiver circuit activates one or more of the multiple subcircuits.

A method for flexibly adjusting the bit rate within a computer network with at least one first node, wherein the node exchanges information via a data bus and / or a point-to-point connection, wherein the steps of - acquiring information about the first reception time of a first message, - receiving information about the first transmission time of the first message, - acquiring information about the second reception time of a second message, - receiving information about the second transmission time of the second message, - determining a first value depending on the received and acquired information, and - comparing the first value with a predetermined second value, - recognizing a state of the first node depending on the comparison result, are performed, characterized in thatthat the comparison result determines a clock generator for generating clock signals of at least the first node and the bit rate present via the data bus and / or via the point-to-point connection to and from the first node and to other nodes in the computer network, and that, if the bit rate is known, the bit rate in the computer network can be flexibly changed by modifying the clock generator for generating the clock signals.

An integrated circuit with an interface circuit is described. During operation, the interface circuit may receive signals corresponding to a header of a frame that is compatible with a serial communication protocol, where the received signals include a temporal pattern of binary bits with instances of a dominant signal level and a recessive signal level. Then, the interface circuit may compute a set of conditions based at least in part on the receive signals, where, when valid, the set of conditions identify a first dominant bit in the binary bits having the dominant signal level. Moreover, when the set of conditions are valid, the interface circuit may: determine a location of synchronization field in the header relative to the identified first dominant bit; and calculate a baud rate of the receive signals based at least in part on a subset of the binary bits in the synchronization field.

Methods and systems for an adaptive modem for wireless devices, comprising, among other things: receiving a wireless signal transmitted by an access point, identifying waveform characteristics of the wireless signal, determining, based on the waveform characteristics, whether the wireless signal contains beacon information, determining, based on the waveform characteristics, a wireless standard for the wireless signal in response to determining that the wireless standard implemented by the wireless signal is a first type of wireless standard and that the wireless signal contains beacon information, obtaining a first pre-trained weight set for the first type of wireless standard, applying the first pre-trained weight set to a first machine learning (ML) model to configure the first ML model for the first type of wireless standard, and restoring,using the first ML model configured for the first type of wireless standard, one or more bits of the beacon information from the wireless signal.

The application relates to a symbol rate calculation method for a phase amplitude modulation mode, which uses a density clustering and statistical method to calculate the symbol rate according to the self characteristics of a radio phase amplitude modulation mode signal; specifically, a signal forward difference sequence of a phase is subjected to statistical analysis to find a suspected symbol position threshold in a distance sequence, suspected symbols whose positions are greater than the suspected symbol position threshold are found, the suspected symbols are counted and an interval sequence is reconstructed, then clustering calculation is adopted, and finally the symbol rate is obtained. A device for the symbol rate calculation method for the phase amplitude modulation mode and a storage medium are also disclosed. The application has the beneficial effects that even if noise exists in the signal, the calculation accuracy of the symbol rate is not affected, and the application has strong practicability and robustness.

The invention relates to a PS-OFDM signal adaptive equalization method based on transfer learning. The method comprises the following steps: taking a PS-OFDM signal which is generated by a transmitting end and has a first shaping rate as a training sample, and training a pre-constructed neural network model by using the training sample to obtain a basic equilibrium model; extracting specific features of PS-OFDM signals of other target forming rates, and performing parameter fine tuning on the basic equalization model by using the specific features to obtain a target equalization model corresponding to each target forming rate; and a receiving end receives the PS-OFDM signal, pre-processes the PS-OFDM signal, calls the corresponding equalization model according to the shaping rate of the signal to carry out nonlinear distortion correction on the pre-processed PS-OFDM signal, and carries out PS inverse transformation recovery to obtain an original bit sequence. By adopting the method provided by the invention, the compatible equalization of the multi-rate PS-OFDM signal can be realized in the hybrid RoF-UOWC system.

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate pre-encoded data, and a transmitter configured to transmit the pre-encoded data through a transmission channel, and a second device including an integrator configured to perform integration on the pre-encoded data, integration samplers including a plurality of samplers configured to output sampled data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the pre-encoded data and a clock based on the decoded data and an output of another one of the samplers.

To restrain diagnosis time from being increased.SOLUTION: A vehicle 10 comprises a vehicle control ECU 12 which is provided with a recording part 18 which records result or the like of self-diagnosis as diagnosis data, and a gateway ECU 13. The gateway ECU 13 includes function which outputs diagnosis data to a diagnostic tool 21 of on the outside of the vehicle when diagnosing the vehicle 10, function which measures communication speed when outputting the diagnosis data to the diagnostic tool 21, function which determines whether or not to execute prior transmission of the diagnosis data on the basis of measured result of the communication speed and function which transmits the diagnosis data to a management server 19 on the outside of the vehicle through radio communication in advance when it is determined to execute the prior transmission.SELECTED DRAWING: Figure 1

The application relates to a PS-OFDM signal adaptive equalization method based on transfer learning. The method comprises the following steps: taking a PS-OFDM signal with a first shaping rate generated by a transmitting end as a training sample, training a pre-constructed neural network model by using the training sample, and obtaining a basic equalization model; extracting unique features of PS-OFDM signals with other target shaping rates, fine-tuning the parameters of the basic equalization model by using the unique features, and obtaining target equalization models corresponding to the target shaping rates; a receiving end receives PS-OFDM signals, and performs pretreatment; according to the shaping rate of the signals, a corresponding equalization model is called to correct the nonlinear distortion of the pretreated PS-OFDM signals, and then the original bit sequence is recovered through PS inverse transformation. By adopting the method, compatible equalization of multi-rate PS-OFDM signals can be realized in a hybrid RoF-UOWC system.

A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. Embodiments of the receiver circuit include a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors the frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust the frequency of the clock signal.

Disclosed is a platform-agnostic 5G Distributed Unit (DU) Physical Layer (PHY) application deployable on general-purpose processors (GPPs) across multiple CPU architectures. The disclosed system decouples DU software from specific hardware platforms by utilizing SIMD abstraction and substitution libraries that enable portable vectorized signal processing. The PHY application may be deployed on both x86-based and Arm-based processors from a single source codebase. In-memory signal processing techniques minimize latency by managing data through pointers and performing operations in registers. The architecture supports containerized deployment and enables operators to select hardware components tailored to their requirements while maintaining functional equivalence across platforms. The disclosed approach may provide energy efficiency benefits through flexible processor selection.

This application provides a method and an apparatus for adjusting a transmission rate, a processor, a network device, and a system. The method includes: obtaining first data at a first rate; adding additional data to the first data in a specific proportion to obtain second data; and sending the second data at a second rate, where the second rate is greater than the first rate. A transmission rate is increased by adding the additional data to the first data in the specific proportion, to break a limitation of a backplane on device capacity expansion and upgrade during device capacity expansion and upgrade. This can not only avoid a frequency hole, but also can meet a future performance requirement.

Circuitry may enable communication between a primary device and one or more secondary devices. The communications may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information about the Baud rate of the secondary device. The UART may operate in a reversed polarity mode, and the reversed polarity may be interpreted by the secondary device as a request to enter an automatic baud detection mode. Entering the automatic baud detection mode using the reversed polarity mode may prevent excessive delays in UART communications and may prevent the need for additional pins to implement the automatic baud detection mode.

Methods and systems for an adaptive modem for wireless devices which includes, among other things, receiving a wireless signal transmitted by an access point, identifying waveform characteristics of the wireless signal, determining, based on the waveform characteristics, whether the wireless signal contains beacon information, determining, based on the waveform characteristics, a wireless standard for the wireless signal, responsive to determining that the wireless standard implemented by the wireless signal is a first type of wireless standard and that the wireless signal contains beacon information, obtaining a first pre-trained weight set for the first type of wireless standard, applying the first pre-trained weight set to a first machine learning (ML) model to configure the first ML model for the first type of wireless standard, and recovering, using the first ML model configured for the first type of wireless standard, one or more bits of the beacon information from the wireless signal.

The vehicle includes a vehicle control ECU including a recording unit that records a self-diagnosis result and the like as diagnostic data, and a gateway ECU. The gateway ECU has a function of outputting diagnostic data to a diagnostic tool outside the vehicle when diagnosing the vehicle, a function of measuring a communication speed when outputting the diagnostic data to the diagnostic tool, a function of determining whether to perform advance transmission of the diagnostic data on the basis of a measurement result of the communication speed, and a function of performing advance transmission of the diagnostic data to a management server outside the vehicle through wireless communication when it is determined that the advance transmission is performed.

Disclosed is a platform-agnostic 5G Distributed Unit (DU) Physical Layer (PHY) application deployable on general -purpose processors (GPPs) across multiple CPU architectures. The disclosed system decouples DU software from specific hardware platforms by utilizing SDMD abstraction and substitution libraries that enable portable vectorized signal processing. The PHY application may be deployed on both x86-based and Arm-based processors from a single source codebase. In-memory signal processing techniques minimize latency by managing data through pointers and performing operations in registers. The architecture supports containerized deployment and enables operators to select hardware components tailored to their requirements while maintaining functional equivalence across platforms. The disclosed approach may provide energy efficiency benefits through flexible processor selection.

A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit that generates an equalized signal, a clock generator circuit that generates a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit monitors a frequency of the clock signal and generates an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. The clock generator circuit uses the indication signal to adjust a frequency of the clock signal.

A method includes obtaining first data at a first rate, wherein the first data is encoded using a first forward error correction (FEC) code type, encoding the first data according to a second FEC code type to obtain second data, adding an amount of additional data in a specific proportion to the second data to obtain third data, wherein the amount of additional data is based on a ratio of a second rate of sending the third data to the first rate of obtaining the first data, and wherein the second rate is greater than the first rate, and sending the third data at the second rate.