5 results about "Serial line" patented technology

An integrated circuit may include a phase shifting / partial beamforming network circuit and a plurality of true time delay (TTD) circuits. The beamforming circuit may include a plurality of receive inputs. Each receive input may be coupled to one of a plurality of antenna elements. The beamforming circuit may include a plurality of receive / transmit connectors, each of which may correspond to a beam of a plurality of beams. The beamforming circuit may include a plurality of transmit outputs each of which may be coupled to one of the plurality of antenna elements. Each TTD circuit may include a first connection coupled to one of the receive / transmit connector outputs and a second connection coupled to one of a plurality of serial lines. Each TTD circuit may be configured to apply one or more of an integer delay or a fractional delay to data received from the receive / transmit connector or the serial line.

The invention discloses a cluster control system and equipment based on an SWD interface and a storage medium, and relates to the technical field of electronic equipment control, and the cluster control system comprises a control node, at least one controlled node and a communication network. The control node comprises a resource scheduling and task management module, a debugging access port control module and an instrument tracking data receiving module; the controlled node comprises a task execution module and an instrument tracking data sending module; and the communication network is a physical communication link based on a serial wire debugging SWD interface, is used for connecting the control node and all the controlled nodes, and is configured to multiplex a debugging access port of the controlled nodes as a communication channel during operation. And communication coordination is complex, and high real-time performance and complex calculation are difficult to consider at the same time.

The present application relates to FPGA technical field, specifically relates to a kind of minimum FPGA CPU verification system and method, including by CPU, RAM and UART composition FPGA end and be equipped with control software controller software PC end, the UART port of the FPGA end is connected with the serial port of the PC end by serial line, when working, FPGA end CPU power-on bootcode, bootcode code cyclically waits UART data.PC end Controllersoftware sends command, is given UART by COM mouth.Transmission.FPGA end CPU receives the data of UART, executes the processing function of corresponding command.The FPGA CPU verification system of the present application is extremely simple, only CPU, UART, RAM can be composed, and has the convenient characteristics of updating test program, has very strong market application prospect.

The invention discloses a multi-host RPA coordination control terminal, which comprises standalone version RPA software deployed on a micro control host, the micro control host is connected with a camera through a USB cable, the camera is aligned with a target host display screen, the micro control host is connected with an identity authentication module through a USB cable, and the identity authentication module is connected with an identity authentication module through a USB cable. The keyboard and mouse integrated interface module is connected with a plurality of target hosts through USB cables on one hand, and is connected with the micro control host through a serial port line on the other hand, and the operation panel is connected with the micro control host through a USB cable; by means of the device, the purposes of flexible arrangement, high adaptability, small occupied space, convenient use, high response speed and reliable control are achieved.

This disclosure provides a memory device and an operational method thereof for performing multiply-accumulate operations. The memory device includes: at least one memory string, multiple data lines, and a serial line. The memory string includes multiple memory cells. Each memory cell has multiple stored values. The multiple data lines are respectively connected to the multiple memory cells to receive multiple data signals. The multiple data signals have multiple input values. When the multiple data signals are input to the multiple memory cells, multiple nodes between the multiple memory cells are at the same voltage level. The serial line is connected to at least one memory string to receive a sensing signal and obtain a measured value. The measured value represents the sum of the products of these input values ​​and these stored values. The multiple data signals and the sensing signal are received at different times.