Method for high speed SATA interface data recovery and serial-parallel conversion and circuit module

Abstract

The high speed SATAn interface data restoring and serial-parallel conversion method includes the following steps: inputting high speed serial signal to obtain four ways of frequency-lowering shunt signal; sampling the four ways of frequency-reducing shunt signal separately; generating one clock signal from the serial line for subsequent sync circuit; outputting integrated sample signal in each clock period; eliminating excessive bits of the sample signal in each clock period and connecting effective bits to constitute bit sequence datan output; comparing the bit sequence datan and the sync word of the protocol for aligning bits and outputting effective protocol data. The circuit module based on the method includes frequency-reducing shunt circuit, successively connected four circuits of sample circuit, integrating output circuit, clock generator circuit and redundant bit eliminating circuit, as well as bit aligning circuit and micro controller.

Description

technical field [0001] The invention relates to data processing, in particular to a method for recovering high-speed SATA interface data and a serial-to-parallel conversion circuit and a circuit module. Background technique [0002] With the development of information technology, the requirements for high bandwidth and easy connection are constantly increasing, thus prompting the rapid development of high-speed serial bus acquisition. The development from USB1.1 to USB2.0, from PATA to SATA, and from PCI to PCI-Express shows that high-speed serial interconnection has become a major development hotspot in the computer field. Specifically, in the design of the high-speed serial ATA bus interface integrated circuit, the time information of the transmitted bits is used to recover the data from the high-speed serial line and complete the conversion from serial to parallel. [0003] Traditional parallel buses mostly use source synchronous clocks, and clocks and data are sent simu...

AI Technical Summary

Problems solved by technology

However, since a large number of redundant signals are sampled, a large number of circuits for removing redundant bits are required for post-processing, and the circuit scale is relatively large.

And as the transmission rate continues to increase, the high-speed local clock signal used for sampling is also a difficult point in the design

[0007] It overcomes the defects of too long phase locking time and too large circuit scale in the prior art, and can effectively improve the tolerance of random data offset, and better complete serial data recovery and serial data to parallel data conversion, It is a technical problem to be solved

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