62 results about "Sync word" patented technology

With audio data reduction on the basis of ISO/IEC standard 11172-3, a frame length varying by 8 bits is used at a sampling frequency of 44.1 kHz in order to arrive, on average, at a particular fixed data rate. The lengthening of a data frame is signalled by a padding bit in the header of the frames. The invention dispenses with evaluation of the padding bit. Instead, the mean frame length L is calculated, L is rounded down to the next integer, for the subsequent frame it is first established whether the expected sync word for this frame appears, and, if this is so, this frame is decoded without taking into account the padding bit, but if the expected sync word for this frame does not appear, the decoding of the frame is started one 8-bit later without taking into account the padding bit.

In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

There is provided an apparatus and method for generating a frame sync word and verifying the frame sync word in an asynchronous CDMA communication system. In the apparatus for generating a sync word for synchronization of frames each having a predetermined number of slots, each of at least two m-sequence generators generates the predetermined number of sequential elements, and a selector multiplexes the sequential elements received from the m-sequence generators and assigns the multiplexed elements in the slots.

A method and apparatus are provided for implementing enhanced data channel performance using a read sample buffer in a direct access storage device (DASD). Disk data is read and stored in the read sample buffer. When a data recovery procedure (DRP) starts, the stored disk read data in the read sample buffer is detected. Error correction code (ECC) checking of the detected sample buffer disk data is performed to identify correctly recovered data. Using the disk read data stored in the read sample buffer enables data recovery without identification of a sync word. Also using the disk read data stored in the read sample buffer enables data recovery with changed channel data detection settings to recover the data. The read sample buffer can be used for accumulating read disk data from more than one read operation so that at least some channel noise is averaged out.

A correlation between a received signal and a sync word signal is calculated. A window signal having a time span which is equal to an equalization range for an adaptive equalizer is defined. A power sum of the correlation output signal in each of window signals #1, #2, #3, . . . are calculated by sequentially shifting the window signal in the time domain, and a rising edge of the particular window signal whose power sum maximum defines a symbol sync timing.

Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

A method and system for communicating signal data in GNSS system using LDPC convolution codes. The method involves, at transmitting end, formatting signal data into a set of subframes. Each subframe of the signal data can be encoded in accordance with a parity check matrix defining Tanner graph representation of LDPC convolution codes. The encoded signal data can be interleaved and added with a Sync word field to transmit an interleaved block of encoded signal data through a communication channel. At receiving end, the interleaved block of encoded signal data can be de-interleaved after it is received from the communication channel. The Tanner Graph shows the connectivity in time invariant parity check matrix. A message passing technique is used to decode the LDPCCC encoded message. The encoded signal data can be decoded through the message passing technique to obtain the signal data primitively transmitted at the transmitting end. Such method and system are capable of achieving error free performance over the GNSS communication channel for effective navigation data communication, and also provide good BER performance over a wide range of Signal-to-Noise ratios.

The portion of TDMA frames otherwise containing the sync word is eliminated for one or more data frames at the end of a TDMA data burst to provided added bandwidth for data payload or for a reduced bandwidth. Once a communication channel has been established and is in steady state mode (after receipt of one or more frames), the sync word is eliminated from the remaining frame structure. Drift of a local clock with respect to an incoming data stream is monitored using an oversampled or multiplied master clock to provide suitable resolution to determine an approximate position of an active edge of the master clock with respect to a bit or symbol being clocked. Any drift from center results in an adjustment of the local master clock. In a preferred embodiment, the drift is measured in a last bit or symbol of a received TDMA burst, and the master clock is adjusted to re-center the local master clock with respect to that last bit. Accordingly, the receiver is "tuned' to the clock signal of the transmitting TDMA device such that the receiving TDMA device can predict where the next start of frame will occur. By doing so, the sync word is no longer necessary in the remaining frames of the TDMA burst to decode the start of next TDMA frame. The sync word may be included in more than one frames in the beginning of the TDMA burst, but is eliminated from one or more frames at the end of the TDMA burst.

A receiver arrangement including a received data reproducing device includes an RF (Radio Frequency) receiver configured to determine the signal strength of a received signal and feed it to a clock frequency determining circuit. Number-of-error information, included in the outputs of a clock phase detector and produced during error detection effected with a sync word, a packet header and a payload of a packet field by field, are also fed to the clock frequency determining circuit. The clock frequency determining circuit designates a subject to deal with the packet and selects single clock frequency information out of clock frequencies determined. The clock frequency information thus selected is input to the clock phase detector.

Both a pre-word (PW) and a sync word (SW) are used to establish a synchronization or only the sync word (SW) is used to establish a synchronization in accordance with an operational status related to the synchronization in a mobile wireless communication apparatus. For example, during an initial synchronization with a control channel (110) being received, both the pre-word (PW) and the sync word (SW) are used to establish a synchronization when a calculation result in a synchronization calculating part exceeds a predetermined threshold value only once. During an initial synchronization with a direct communication channel (112) being received, both the pre-word (PW) and the sync word (SW) are used to establish a synchronization when the calculation result exceeds the predetermined threshold value once; or alternatively, only the sync word (SW) is used to establish a synchronization when the calculation result successively exceeds the predetermined threshold value twice. According to the present invention, the sync word is shortened so as to quickly establish a communication link, and the sync detection can be performed with high precision.

Provided is a method for detecting frame sync and frame structure in a satellite broadcasting system, which acquires an estimated value for detecting frame structure and frame sync and overcomes distortion of correlation analysis values by summing differential correlation values for SOF positions in consideration of the variable frame length, and selecting a maximum value in a channel environment with low signal-to-noise ratio and high frequency error. SOF is a sync word indicating the start point of a frame. The method includes the steps of: acquiring SOF differential correlation value sequences; acquiring sums (d_i,t) of the correlation values normalized for SOF positions based on the number of symbols per frame by using the above-generated SOF differential correlation value sequences; and selecting a maximum value (d_z,x) among the sums of correlation values, detecting z as a frame sync position, and detecting x as a frame structure index.

The high speed SATAn interface data restoring and serial-parallel conversion method includes the following steps: inputting high speed serial signal to obtain four ways of frequency-lowering shunt signal; sampling the four ways of frequency-reducing shunt signal separately; generating one clock signal from the serial line for subsequent sync circuit; outputting integrated sample signal in each clock period; eliminating excessive bits of the sample signal in each clock period and connecting effective bits to constitute bit sequence datan output; comparing the bit sequence datan and the sync word of the protocol for aligning bits and outputting effective protocol data. The circuit module based on the method includes frequency-reducing shunt circuit, successively connected four circuits of sample circuit, integrating output circuit, clock generator circuit and redundant bit eliminating circuit, as well as bit aligning circuit and micro controller.

The invention relates to a method for synchronizing data frames. The method comprises the following steps: capturing sync words in the data frames, and outputting a capture indicator signal and a capture sync word serial number; according to the capture indicator signal, the capture sync word serial number and a current count value, executing multiplex synchronization lock, computing and latchingthe frame head position, and outputting a locked signal and an empty/full indicator signal, wherein the count value is obtained by executing a cycle count taking a frame length as a cycle to the received data frames, the empty/full indicator signal comprises an empty state and a full state respectively indicating unlatched and latched; according to the locked signal, outputting a locking indicatorsignal, outputting a frame head indicator signal according to the current count value, and outputting a write enable signal according to the empty/full signal, wherein the write enable signal is usedfor coordinating the multiplex synchronization lock. The invention achieves a fast, exact and stable data frame synchronizing method.

A method and apparatus for synchronization of a moving picture experts group (MPEG) transport stream, which minimizes an initial delay are provided. A packet synchronization unit and a mode of the packet synchronization unit to are initialized to “0”. Values of sync words are stored by shifting values of a sync word register when the sync words have been received and the received sync word is compared with predetermined code words As a result of the comparison, a determination is made as to whether a bit difference between the sync words and the predetermined code words exceeds a predetermined threshold value. A verification is then made as to whether all bits of the sync words correspond to all bits of the predetermined code words, when it is determined as a result of the determination that the bit difference is less than or equal to the predetermined threshold value and the MPEG transport stream is descrambled before returning to step of storing values of sync words by shifting values of a sync word register.

A frame synchronization apparatus and method based on differential correlation in a communication system are provided. A correlation analysis is performed by using sync word in a prior search window and a posterior search window for obtaining a plurality of prior-window correlation values and a plurality of posterior-window correlation values, respectively. N maximum correlation values in the correlation values are selected, wherein indexes of the maximum correlation values are I₁˜I_N, and N is an integer greater than 0. The posterior-window correlation values are compared with a first threshold. If one of the posterior-window correlation values is greater than the first threshold, the index of the one is defined as J. If the index J is equal to one of the index I₁˜I_N, a check step is performed by using the index J for confirming that a position of the index J is a header position.

In a transmitter, a motion detector detects a motion amount of a coded block. A buffer memorizes a detected motion amount. A buffer controller controls the buffer to read the motion amounts in the order opposed to the writing order. A switch selects one of outputs. In a receiver, a sync word detector discriminates first and second sync words. A primary frame memory memorizes an actually decoded image. A secondary frame memory memorizes a predicted image corresponding to the actually decoded image. Memory controllers read out the image information of coding blocks from the corresponding frame memories in an order opposed to the writing order. A switch selects either one of the information of the primary or secondary frame memories.

In a channel estimating circuit, a Sync Word is demodulated by using a channel estimation value not with a symbol or a slot including the Sync Word to be demodulated, but with its preceding and succeeding symbols or slots. Furthermore, in a channel estimation process, if a Synch Word to be demodulated is included in any of groups into which a plurality of symbols are divided, the Sync Word is demodulated by using a channel estimation value obtained with the channel estimation process using not this group but another group.