66 results about "Underclocking" patented technology

The invention relates to the technical field of chip heat dissipation, and provides an immersed heat dissipation system with liquid nitrogen as a cooling medium and an integrated circuit assembly. In an immersed heat dissipation system with liquid nitrogen as a cooling medium, huge heat generated by a high-power-density chip under an extreme working condition can be efficiently absorbed and taken away under the extremely low working temperature and the large phase change heat absorption capacity, the heat transfer limit of a traditional cooling technology is broken through, and deep cooling of the chip is achieved; meanwhile, the liquid nitrogen is non-conductive and stable in chemical property, the electrical short circuit risk and physical and chemical corrosion problems caused by leakage of the cooling working medium are thoroughly eliminated, and the long-term operation reliability and safety of the immersed heat dissipation system with the liquid nitrogen as the cooling medium are remarkably improved. Therefore, stable operation of the chip under high load is guaranteed, physical damage and performance frequency reduction caused by overheating are avoided, and even favorable conditions are created for safe and efficient operation of the chip under higher working frequency.

The invention discloses a method for heterogeneous scheduling of computing power under a large model training reasoning framework, relates to the technical field of computing power scheduling, and solves the technical problem that task interruption or resource waste is easily caused by incomplete task migration, splitting and recovery mechanisms when computing power is insufficient or equipment is abnormal. According to the method, parameters such as the load rate, the residual computing power and the temperature of the CPU, the GPU and the FPGA are dynamically collected, the calculation amount, the duration and the delay requirement of the task are combined, a quantitative model is established, the resource utilization rate is increased, a temperature prediction model is established in stages, a dynamic threshold value is set in combination with the equipment type, the environment temperature and the health degree, temperature early warning and migration in the task execution process are achieved, and the task execution efficiency is improved. The frequency reduction risk caused by overheating of equipment is reduced, the task interruption loss is ensured to be reduced by more than 50% through task splitting, intelligent migration and pause recovery mechanisms aiming at insufficient computing power or equipment abnormity, and the stability of the system during peak flow or hardware failure is improved.

The invention discloses an LLC circuit and a control method and device thereof, a power conversion system, a storage medium and a computer program product, the LLC circuit is provided with an LLC resonant cavity and a switching tube module, and the switching tube module is provided with a first switching tube and a second switching tube which can be alternately conducted up and down; the control method of the LLC circuit comprises the following steps: acquiring a preset resonant current threshold value of the LLC resonant cavity; and under the condition that the LLC circuit starts to start after being electrified, on the basis of a resonant current threshold value of the LLC resonant cavity, asymmetric driving pulse starting is firstly performed on the switching tube module, and then frequency reduction starting is performed, so that current-limiting starting control of the LLC circuit is realized. According to the scheme, after the LLC circuit is powered on, asymmetric driving pulse starting is firstly carried out on the switching tube module, and then frequency reduction starting is carried out, so that current-limiting starting control of the LLC circuit is realized, and the LLC circuit is enabled to be stably and safely started.

The invention discloses a temperature control power supply collaboration method and electronic equipment, and relates to the technical field of temperature control power supply collaboration, and the method comprises the steps: collecting node current data and node temperature data of a plurality of node servers in real time, and the capacitance state information of a capacitor unit; calculating an output phase difference of the power supply unit according to the node current data, the node temperature data and the capacitance state information, and generating a first output current distribution parameter; determining a first heat dissipation control parameter of a heat dissipation execution unit according to the node temperature data; and carrying out conjoint analysis on the first output current distribution parameter and the first heat dissipation control parameter to obtain a temperature-electricity cooperative adjustment amount, and generating a second output current distribution parameter and a second heat dissipation control parameter. Dynamic coupling optimization of power supply and temperature control in the server case can be achieved, stable and balanced distribution of the temperature and the current of the node server is guaranteed, and the problems that in the related technology, instantaneous over-temperature of the nodes causes frequency reduction protection, and temperature and current distribution between the nodes is not uniform are solved.

The invention belongs to the technical field of thermal management and performance regulation and control of a computer hardware system, and particularly discloses a temperature and performance coordinated regulation and control method of an MODT mainboard central processing unit. The entropy production rate of the system is calculated in real time in combination with a thermodynamic entropy production evaluation mechanism, and pre-cooling or advanced frequency reduction pulse type regulation and control are triggered when entropy production exceeds the threshold; meanwhile, a biological rhythm simulation mechanism is introduced, high-frequency and low-frequency alternating periodic oscillation control is carried out on the frequency of the processor in a millisecond-level window, the two mechanisms cooperatively act on the power management unit, and microsecond-level voltage regulation and heat dissipation driving linkage is achieved. According to the technical scheme, on the premise that the hardware cost is not increased, the energy efficiency performance, the transient heat dissipation capacity and the long-term operation reliability of the system under the high dynamic load are improved.

This invention relates to a thermal control method for grid-connected converters that balances low harmonics and junction temperature limitations, belonging to the field of intelligent power electronics control. It employs a DPWM modulation method that locks the optimal clamping interval under overload conditions and couples this method with switching frequency control. Offline simulation is used to scan the switching frequency, obtaining data on the peak junction temperature and grid current variations as a function of the switching frequency, which is then stored in a lookup table accessible to the controller. During operation, feasible switching frequency ranges are selected based on junction temperature and dual constraints, and a recommended switching frequency range is provided. Within the acceptable frequency range, the optimal frequency reduction point is selected according to a proposed selection function, thus achieving a dynamic trade-off between thermal safety and system performance during overload. This invention, by fully considering the coupling effect of DPWM and frequency reduction, provides the optimal operating frequency point to ensure the safe and compliant operation of the converter under overload conditions.

The invention provides an equipment control device and method and electronic equipment, relates to the field of computers, and can quickly respond to and control frequency reduction of a processor when the processor in first equipment quickly releases sudden power consumption, thereby reducing the risk of overload of a system power supply or power failure of the first equipment and improving the power supply safety of the system power supply. The device comprises a first hardware module and a second hardware module. The first hardware module is respectively connected with a power supply link of the first equipment and a processor of the first equipment, and the second hardware module is respectively connected with the power supply link and the processor. The first hardware module is used for acquiring the voltage of the power supply link in real time and triggering the processor to reduce frequency through hardware interruption when the voltage is within a first range. An upper bound of the first range is less than a nominal voltage of the first device. And the second hardware module is used for acquiring the current of the power supply link in real time and triggering the processor to reduce frequency through hardware interruption when the current is within a second range. The lower bound of the second range is greater than the ratio of the rated power to the nominal voltage of the first device.

This invention relates to the field of computer peripheral control, and more particularly to a method and system for monitoring and controlling the status of computer peripherals. The method includes the following steps: acquiring an internal load sequence and an external current sequence; calculating a first-order difference term using a sliding window; accumulating and weighting the products of the first-order difference term, the external current sequence, and a preset reference voltage to obtain a transient power supply deficit gradient; acquiring a retransmission count sequence; and weighting and accumulating the cross product of the transient power supply deficit gradient and the retransmission count sequence, along with their first-order moment statistical characteristics, to obtain a latent current outage risk index; acquiring service priority weights; and mapping the latent current outage risk index to the service priority weights to obtain a stability degradation diagnostic signal; and calculating a frequency reduction control factor and adjusting the operating state when the stability degradation diagnostic signal exceeds a preset threshold. This invention effectively identifies latent current outage faults, achieving accurate diagnosis and adaptive control.

The application discloses a method for power heterogenous scheduling under a large model training and reasoning framework, and relates to the technical field of power scheduling. The application solves the technical problem that the task migration, splitting and recovery mechanism is imperfect, and task interruption or resource waste is easily caused when facing insufficient computing power or device abnormity. The application collects the load rate, residual computing power, temperature and other parameters of CPU, GPU and FPGA dynamically, establishes a quantitative model in combination with the calculation amount, time length and delay demand of the task, improves the resource utilization rate, establishes a temperature prediction model in stages, sets a dynamic threshold in combination with the device type, environmental temperature and health degree, realizes temperature warning and migration in the task execution process, reduces the risk of frequency reduction caused by device overheating, and ensures that the task interruption loss is reduced by more than 50% through the task splitting, intelligent migration and suspension recovery mechanism, thereby improving the stability of the system in peak traffic or hardware failure.

The application provides a valley function module control circuit, a control method, a switching power supply and a controller, and solves the problem of low reliability of a quasi-resonant switching power supply with a valley lock function. The valley function module control circuit comprises a generation module and an updating module. The generation module is configured to determine a real-time working state signal based on a feedback voltage; when the real-time working state signal is a first working state signal, it is determined that the working state signal is switched between an nth valley lock state signal and a frequency reduction state signal, and the working state signal at the current time is maintained until a preset condition is met; the working state signal at the current time is updated based on the feedback voltage, and the updated working state signal is output; the first working state signal comprises the nth valley lock state signal and the frequency reduction state signal; and the updating module is configured to update the selected working state signal of the current switching period based on the updated working state signal, so as to control the opening position of the power tube in the next switching period.

The application discloses an automatic server detection management device, and relates to the technical field of servers, comprising a server body, wherein a cooling structure is fixedly installed at the bottom of the server body, and a ventilation structure is fixedly installed at the bottom of the cooling structure. The automatic server detection management device can realize real-time monitoring of the internal temperature of the server body through a temperature sensor, linkage control of the opening and closing of a water pump, and driving of low-temperature cooling liquid in a semiconductor refrigeration pre-cooling cooling liquid bin to be shunted through a tee pipe and then be targetedly supplied to high-heat-conducting copper heat dissipation fins at the bottom of a CPU and a GPU. The heat dissipation fins are designed in a continuous bending mode of a Tesla valve shape, so that the effective heat dissipation area is multiplied in a limited space, airflow is induced to form high-strength vortex, and the thermal resistance boundary layer is completely broken, so that targeted cooling of key heat sources is realized, the risk of hardware frequency reduction caused by local overheating is eliminated from the root, and the stability of continuous full-load operation of the server is ensured.

The invention discloses an NPU-based edge computing video stream processing method and system. The method comprises the steps of video stream data acquisition and writing-in, zero-copy hardware preprocessing, model loading and asynchronous reasoning and result acquisition and post-processing. According to the method, a'control-calculation 'hardware-level decoupling architecture is constructed, and a special NPU is started to execute reasoning, so that the load and the power consumption of a CPU are greatly reduced, and the problems of frequency reduction and dead halt of a system caused by overheating of the CPU are thoroughly solved. A full-link zero-copy data channel based on DMA and RGA hardware is established, so that the video stream processing delay is remarkably reduced, and stable real-time analysis under a high frame rate is realized. By adopting the operator fusion and INT8 hybrid quantization technology, the calculation and memory access efficiency of the model on the NPU is multiplied, and higher energy efficiency ratio and throughput are obtained while the precision is ensured. Finally, the edge equipment can stably run at low temperature for a long time in a closed environment without fan heat dissipation.

This invention discloses an overclocking simulation calculation method for heat dissipation modules, applied to the optimal prediction of overclocking / downclocking factors and times for heat pipe and other heat dissipation modules. New-generation AIPC chips, in order to achieve higher computing performance, have built-in powerful overclocking capabilities. However, when paired with existing heat pipe heat dissipation modules, an optimal combination of overclocking factor and time is needed to maximize the computing performance of the built-in overclocking function. Higher overclocking factors result in better performance, but the overclocking time must be shorter; the frequency must be reduced before reaching the chip's temperature limit to avoid exceeding the chip's temperature range. Therefore, by simulating the combination of parameters such as overclocking factor, overclocking time, downclocking factor, and downclocking time using equations, without exceeding the chip's temperature limits, development costs can be significantly reduced.

The application discloses a segmented soft-start control method for forward charging of a bidirectional CLLC resonant converter, relates to the technical field of power electronic converter control, and is realized based on an on-board charger (OBC) system, wherein the OBC system comprises a front-stage totem pole PFC rectifier circuit, a CLLC charging and discharging circuit and an auxiliary power supply circuit, the PFC output voltage is used as the CLLC primary bus voltage, the CLLC secondary side output is used for battery charging, and the system is controlled by an external BMS or a host computer. According to the method, a dynamic parameter setting algorithm based on model prediction is adopted, the minimum constant current point under different starting conditions is automatically adjusted, the stability of soft starting under various conditions is realized, the smooth transition of the control mode is ensured in view of the stage switching oscillation problem, the problems of gain mutation at the soft start end time of the initial fixed slope frequency reduction strategy and long soft start time are solved, the gain of the whole soft start process is closer to the gain curve of the converter, and therefore the resonant cavity peak current is further reduced.

The invention provides a frequency reduction processing method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps of determining current first calculation performance data of a processor; determining whether the processor has underclocking according to the first calculation performance data; when frequency reduction of the processor is determined, determining a target frequency reduction level according to the first calculation performance data; and closing at least one service corresponding to the target frequency reduction level. According to the method and the device, whether the processor has underclocking or not can be detected based on the first calculation performance data, and corresponding service closing can be realized according to the current underclocking level when underclocking occurs, so that the influence of underclocking of the processor on AI core service operation can be reduced, stable operation of a system can be effectively guaranteed, and the service quality of the AI core service is improved. And user experience is improved.

The invention relates to a network construction type converter thermal control method considering low harmonic waves and junction temperature limitation, which belongs to the field of power electronic intelligent control, and comprises the following steps: locking a DPWM modulation mode of an optimal clamping interval under an overload condition, and carrying out coupling design with switching frequency control; switching frequency is scanned through off-line simulation, data of device peak junction temperature and grid-connected current changing along with the switching frequency are obtained respectively, and the data are solidified into a lookup table capable of being called by a controller; during operation, a feasible switching frequency interval is screened according to junction temperature and double constraints, a recommended switching frequency interval is given, and an optimal frequency reduction working point is selected according to a provided selection function in the frequency interval meeting requirements, so that dynamic compromise between thermal safety and system performance during overload is realized. According to the method, the optimal operation frequency point is given under the condition of fully considering the DPWM and frequency reduction coupling effect, so that the safe and compliant operation of the converter under the overload working condition is realized.

The invention relates to the field of storage device control, in particular to a temperature adjusting method and device, a storage device and a computer readable storage medium. The temperature adjusting method is used for adjusting the temperature of a flash memory, the flash memory comprises a plurality of memory units storing logic values, and the temperature adjusting method comprises the following steps: obtaining a target reading margin of the flash memory, the target reading margin being a distance between a boundary of a threshold voltage distribution interval of a target memory unit and a target reading voltage, a target logic value is stored in the target storage unit, and the target reading voltage is used for reading the target logic value; a thermal throttling strategy of the flash memory is determined based on the target reading margin, the thermal throttling strategy comprises at least one frequency reduction temperature threshold value, and the higher the target reading margin is, the higher the frequency reduction temperature threshold value is; and if the current temperature of the flash memory rises to the frequency reduction temperature threshold, reducing the working frequency of the flash memory. The performance of the flash memory can be improved on the basis of ensuring the reliability of the flash memory.

This invention discloses a CPU dynamic frequency adjustment method based on multi-level load detection, comprising the following steps: S1, creating three load detection tasks and setting their priorities among different priority levels of real-time operating system tasks; S2, setting different decision cycles for the business characteristics of tasks with different priorities; S3, obtaining the idle level of the corresponding priority task group by detecting whether the three load detection tasks can be scheduled for execution; S4, adjusting the CPU frequency according to the idle level of different priority task groups. By setting load detection tasks among different priority levels of tasks, fine-grained monitoring is achieved, ensuring timely frequency increase for high-priority tasks when resources are insufficient to guarantee real-time performance. The differentiated decision cycle enables millisecond-level rapid response to sudden business events, and the precise perception of load conditions at each level achieves optimal frequency reduction to maximize energy saving, thus achieving a balance between real-time performance assurance and energy efficiency optimization.

The application relates to a low-frequency double-frequency control light-load high-ITHD digital control method, which comprises the following steps: S100, obtaining a PFC switching frequency after frequency reduction; S200, setting a sampling frequency of an inductor current IL of an ADC and a loop operation frequency as twice the PFC switching frequency, and setting an inductor current IL sampling point of the ADC and a loop operation point at positive integer multiples of 1 / 2 of a switching period T; S300, calculating a driving duty ratio D2 of a next switching period T according to a collected sampling current Itrg and a loop operation formula; S400, setting a midpoint of the obtained driving duty ratio D2 of the next period at a midpoint of the next switching period T; and S500, cyclically executing the steps of S300 and S400; the method can greatly improve the problem that an inductor current IL is seriously distorted in a DCM working mode, thereby improving ITHD and PF.

The invention relates to the technical field of power module control, in particular to a self-adaptive junction temperature control power module control method, which comprises the following steps: collecting a junction temperature instantaneous value of a to-be-predicted module, and predicting a residual life decay rate by adopting a long-short term memory model; the switching frequency of the to-be-predicted module is reduced according to the junction temperature change rate, and the junction temperature change rate is collected and generated again; and performing secondary optimization on the switching frequency according to the newly generated junction temperature change rate. In order to solve the problems that a power module control method in the prior art only performs linear control on temperature rise and is poor in life loss optimization, in the scheme, a secondary optimization process is designed for the influence degree of junction temperature fluctuation on the residual life of the power module, firstly, the severe temperature rise is intervened through a simple junction temperature change rate, and then the residual life of the power module is optimized; the further aggravation of temperature rise fluctuation is avoided through a frequency reduction mode, and secondary optimization is carried out on the condition of residual life loss in a long term predicted based on the junction temperature change rate, so that a relatively good control effect on the power module is realized.

The invention provides a performance parameter adjusting method and device, a chip, electronic equipment and a medium, and relates to the technical field of communication. Comprising the steps that based on indication information of network equipment, a target gear interval is determined in multiple sets of candidate gear information of performance parameters of a terminal, the performance parameters comprise frequencies and voltages, and each set of candidate gear information corresponds to a set of voltages and frequencies for a central processing unit and / or at least one hardening accelerator of the terminal; determining a target gear in the target gear interval based on the running state information of the terminal under the current working load; and respectively adjusting performance parameters of the central processing unit and / or the at least one hardening accelerator based on the target gear. According to the method provided by the invention, invalid power consumption can be greatly reduced, and the battery life is effectively prolonged; through adjustment of the determined target gear, severe fluctuation of performance is avoided, jamming caused by instantaneous high load and subsequent temperature control frequency reduction is reduced, and continuous and stable user experience is guaranteed.

The present invention discloses a compressor frequency reduction protection method and a compressor. The compressor includes an IPM hardware circuit having a sampling resistor. The frequency reduction protection method includes: periodically collecting temperature parameters and electrical parameters on the sampling resistor; after the compressor operates stably, performing current frequency reduction protection on the compressor according to the electrical parameters; when the current frequency reduction protection is started and the compressor operates normally, performing temperature frequency reduction protection on the compressor according to the temperature parameters; and enabling the unit to output the maximum refrigerating capacity within the set frequency. Compared with the prior art, the present invention has temperature sampling and current sampling functions, can effectively avoid problems such as large resistance values caused by harsh working conditions and a series of problems such as poor heat dissipation and small copper surface coverage due to process problems, and the problem of false alarms caused by the virtual high sampling current of the IPM hardware circuit.

The invention relates to the technical field of communication, in particular to a dynamic frequency modulation method, a dynamic frequency modulation circuit and a dynamic frequency modulation device suitable for an AXI stream transmission protocol. Effective data sent by a host are temporarily stored in a storage module, whether the effective data are sent to a slave or not is decided according to the state of a downstream slave, and the effective data are transmitted to the slave. Empty packets can be screened out before the data are added into the storage module, only effective data are cached, resources are saved, and meanwhile the data transmission efficiency is improved. The clock frequency signal is determined according to the size of the load, and the clock frequency signal is issued to the slave, so that the slave performs frequency increasing or frequency decreasing according to the clock frequency signal, the purpose of dynamically adjusting the clock frequency according to the upstream and downstream load conditions is achieved, the power consumption of the whole circuit is reduced on the premise of not influencing the performance, and load balancing is achieved; and the bandwidth performance of the system is not lost.

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

The invention relates to a down-conversion serialization output network for testing a high-speed time domain interleaving analog-to-digital converter, which is characterized in that a clock down-conversion module accesses M single-channel sampling clock signals and performs down-conversion processing to obtain M down-conversion clock signals, and the M down-conversion clock signals are transmitted to a clock serialization module and a latch module; the clock serialization module is used for carrying out serialization processing on the M underclocking clock signals to obtain a high-frequency interleaving clock signal and transmitting the high-frequency interleaving clock signal to the output serialization module; the latch module responds to the M underclocking clock signals, performs underclocking latching on M groups of quantized codes input into the M underclocking clock signals, and outputs M groups of underclocking quantized codes of the current period; and the output serialization module accesses the clock serialization signals generated by the clock serialization module in the serialization processing process and the high-frequency interleaving clock signals, and the output serialization module responds to the multiple clock serialization signals and serializes the M groups of underclocking quantized codes to obtain a synthesized quantized code. The device can meet high-speed ADC test requirements.

The disclosure provides a voltage drop control method, which comprises the following steps: obtaining a to-be-executed instruction path; determining whether the to-be-executed instruction path is a marked instruction path; and enabling a preset current limiting strategy to execute the to-be-executed instruction path in the case that the to-be-executed instruction path is the marked instruction path, wherein the current limiting strategy is used to adjust voltage before triggering the voltage drop. The embodiment of the application can suppress voltage drop in advance by suppressing control voltage before the execution of the to-be-executed instruction path, suppress voltage drop with a small performance cost, reduce the triggering probability of frequency reduction for suppressing voltage drop, and further reduce the power consumption gain of the operating voltage of the CPU.

The invention relates to the technical field of power supply circuits, in particular to a module for preventing power failure during plugging and unplugging switching of a round hole adapter and a Type-C adapter. The device comprises an uninterruptible power supply module, a round hole adapter and a Type-C adapter. According to the method and the device, when the circular hole adapter and the Type-C adapter are accessed at the same time, the system is preferentially started by the circular hole adapter; if the round hole adapter is pulled out during operation, the module is quickly grounded through a Switch pin of the module, the system is notified to reduce frequency so as to reduce power consumption, meanwhile, Type-C power supply is seamlessly switched, and shutdown caused by voltage drop is avoided; if the system is only powered by the Type-C originally, after the round hole adapter is inserted, the module automatically cuts off the Type-C after the voltage of the module is stable, and the round hole adapter is switched to preferentially supply power, so that the mechanism not only enables a user to randomly plug and unplug different power supplies without shutdown, but also greatly improves the reliability and operation convenience of continuous operation of equipment.

The invention discloses a frequency source rapid taming locking method and system and a storage medium, and belongs to the technical field of time frequency. The method comprises the following steps: S1, reducing the frequency of an initial reference signal and a measured signal to a target frequency through a frequency divider, and outputting the target frequency to a phase discriminator; s2, the MCU module reads the time difference value measured by the phase discriminator in an SPI mode; s3, calculating relative frequency deviation according to the time difference value; s4, after the relative frequency deviation is obtained through calculation, a frequency control word is adjusted according to the parameters of the local time source to be used for the local time source, and the frequency of the local time source is locked to the frequency of the reference source; s5, the MCU module calculates a phase deviation according to the time difference value and writes the phase deviation into the phase modulator, and finally outputs a preset frequency signal of which the frequency and the phase are synchronized to the reference source; and S6, setting the number of times of repeating the steps S2 to S5 according to requirements, and enabling the signal output by the local time source to be close to the signal of the reference source, thereby finishing taming locking of the local time source. The taming time can be shortened, and the purpose of fast taming and locking is achieved.

This application discloses a temperature-controlled power supply coordination method and electronic device, relating to the field of temperature-controlled power supply coordination technology. The method includes real-time acquisition of node current data, node temperature data, and capacitor status information of multiple node servers; calculation of the output phase difference of the power supply unit based on the node current data, node temperature data, and capacitor status information, and generation of a first output current allocation parameter; determination of a first heat dissipation control parameter of the heat dissipation execution unit based on the node temperature data; joint analysis of the first output current allocation parameter and the first heat dissipation control parameter to obtain a temperature-power coordinated adjustment amount, and generation of a second output current allocation parameter and a second heat dissipation control parameter. This application enables dynamic coupling optimization of power supply and temperature control within the server chassis, ensuring a stable and balanced distribution of temperature and current in the node servers, thereby solving the problems of frequency reduction protection caused by instantaneous overheating of nodes and uneven temperature and current distribution between nodes in related technologies.

The present invention relates to the field of clock frequency modulation technology, and provides a hardware automatic frequency modulation device and method based on clock division and multiplexing. The device includes: a clock source; a frequency modulation control unit for outputting a clock selection signal; a clock frequency division circuit; a selection output; the selection output can output the clock source signal received at the first input end of the selection output or the first clock signal received at the second input end of the selection output according to the clock selection signal received at the control end. The present invention can obtain more low-frequency signals for chip use by dividing a single clock source signal without occupying additional clock source output resources, and further improve the adjustment flexibility of the clock source signal; in addition, the frequency division signal based on the logic circuit has a higher response rate than the software frequency modulation, which can improve the immediacy of chip frequency reduction.