39 results about "Underclocking" patented technology

The invention discloses a method for heterogeneous scheduling of computing power under a large model training reasoning framework, relates to the technical field of computing power scheduling, and solves the technical problem that task interruption or resource waste is easily caused by incomplete task migration, splitting and recovery mechanisms when computing power is insufficient or equipment is abnormal. According to the method, parameters such as the load rate, the residual computing power and the temperature of the CPU, the GPU and the FPGA are dynamically collected, the calculation amount, the duration and the delay requirement of the task are combined, a quantitative model is established, the resource utilization rate is increased, a temperature prediction model is established in stages, a dynamic threshold value is set in combination with the equipment type, the environment temperature and the health degree, temperature early warning and migration in the task execution process are achieved, and the task execution efficiency is improved. The frequency reduction risk caused by overheating of equipment is reduced, the task interruption loss is ensured to be reduced by more than 50% through task splitting, intelligent migration and pause recovery mechanisms aiming at insufficient computing power or equipment abnormity, and the stability of the system during peak flow or hardware failure is improved.

The invention belongs to the technical field of thermal management and performance regulation and control of a computer hardware system, and particularly discloses a temperature and performance coordinated regulation and control method of an MODT mainboard central processing unit. The entropy production rate of the system is calculated in real time in combination with a thermodynamic entropy production evaluation mechanism, and pre-cooling or advanced frequency reduction pulse type regulation and control are triggered when entropy production exceeds the threshold; meanwhile, a biological rhythm simulation mechanism is introduced, high-frequency and low-frequency alternating periodic oscillation control is carried out on the frequency of the processor in a millisecond-level window, the two mechanisms cooperatively act on the power management unit, and microsecond-level voltage regulation and heat dissipation driving linkage is achieved. According to the technical scheme, on the premise that the hardware cost is not increased, the energy efficiency performance, the transient heat dissipation capacity and the long-term operation reliability of the system under the high dynamic load are improved.

This invention relates to a thermal control method for grid-connected converters that balances low harmonics and junction temperature limitations, belonging to the field of intelligent power electronics control. It employs a DPWM modulation method that locks the optimal clamping interval under overload conditions and couples this method with switching frequency control. Offline simulation is used to scan the switching frequency, obtaining data on the peak junction temperature and grid current variations as a function of the switching frequency, which is then stored in a lookup table accessible to the controller. During operation, feasible switching frequency ranges are selected based on junction temperature and dual constraints, and a recommended switching frequency range is provided. Within the acceptable frequency range, the optimal frequency reduction point is selected according to a proposed selection function, thus achieving a dynamic trade-off between thermal safety and system performance during overload. This invention, by fully considering the coupling effect of DPWM and frequency reduction, provides the optimal operating frequency point to ensure the safe and compliant operation of the converter under overload conditions.

The invention provides an equipment control device and method and electronic equipment, relates to the field of computers, and can quickly respond to and control frequency reduction of a processor when the processor in first equipment quickly releases sudden power consumption, thereby reducing the risk of overload of a system power supply or power failure of the first equipment and improving the power supply safety of the system power supply. The device comprises a first hardware module and a second hardware module. The first hardware module is respectively connected with a power supply link of the first equipment and a processor of the first equipment, and the second hardware module is respectively connected with the power supply link and the processor. The first hardware module is used for acquiring the voltage of the power supply link in real time and triggering the processor to reduce frequency through hardware interruption when the voltage is within a first range. An upper bound of the first range is less than a nominal voltage of the first device. And the second hardware module is used for acquiring the current of the power supply link in real time and triggering the processor to reduce frequency through hardware interruption when the current is within a second range. The lower bound of the second range is greater than the ratio of the rated power to the nominal voltage of the first device.

This invention relates to the field of computer peripheral control, and more particularly to a method and system for monitoring and controlling the status of computer peripherals. The method includes the following steps: acquiring an internal load sequence and an external current sequence; calculating a first-order difference term using a sliding window; accumulating and weighting the products of the first-order difference term, the external current sequence, and a preset reference voltage to obtain a transient power supply deficit gradient; acquiring a retransmission count sequence; and weighting and accumulating the cross product of the transient power supply deficit gradient and the retransmission count sequence, along with their first-order moment statistical characteristics, to obtain a latent current outage risk index; acquiring service priority weights; and mapping the latent current outage risk index to the service priority weights to obtain a stability degradation diagnostic signal; and calculating a frequency reduction control factor and adjusting the operating state when the stability degradation diagnostic signal exceeds a preset threshold. This invention effectively identifies latent current outage faults, achieving accurate diagnosis and adaptive control.

The application discloses a method for power heterogenous scheduling under a large model training and reasoning framework, and relates to the technical field of power scheduling. The application solves the technical problem that the task migration, splitting and recovery mechanism is imperfect, and task interruption or resource waste is easily caused when facing insufficient computing power or device abnormity. The application collects the load rate, residual computing power, temperature and other parameters of CPU, GPU and FPGA dynamically, establishes a quantitative model in combination with the calculation amount, time length and delay demand of the task, improves the resource utilization rate, establishes a temperature prediction model in stages, sets a dynamic threshold in combination with the device type, environmental temperature and health degree, realizes temperature warning and migration in the task execution process, reduces the risk of frequency reduction caused by device overheating, and ensures that the task interruption loss is reduced by more than 50% through the task splitting, intelligent migration and suspension recovery mechanism, thereby improving the stability of the system in peak traffic or hardware failure.

The application provides a valley function module control circuit, a control method, a switching power supply and a controller, and solves the problem of low reliability of a quasi-resonant switching power supply with a valley lock function. The valley function module control circuit comprises a generation module and an updating module. The generation module is configured to determine a real-time working state signal based on a feedback voltage; when the real-time working state signal is a first working state signal, it is determined that the working state signal is switched between an nth valley lock state signal and a frequency reduction state signal, and the working state signal at the current time is maintained until a preset condition is met; the working state signal at the current time is updated based on the feedback voltage, and the updated working state signal is output; the first working state signal comprises the nth valley lock state signal and the frequency reduction state signal; and the updating module is configured to update the selected working state signal of the current switching period based on the updated working state signal, so as to control the opening position of the power tube in the next switching period.

The application discloses an automatic server detection management device, and relates to the technical field of servers, comprising a server body, wherein a cooling structure is fixedly installed at the bottom of the server body, and a ventilation structure is fixedly installed at the bottom of the cooling structure. The automatic server detection management device can realize real-time monitoring of the internal temperature of the server body through a temperature sensor, linkage control of the opening and closing of a water pump, and driving of low-temperature cooling liquid in a semiconductor refrigeration pre-cooling cooling liquid bin to be shunted through a tee pipe and then be targetedly supplied to high-heat-conducting copper heat dissipation fins at the bottom of a CPU and a GPU. The heat dissipation fins are designed in a continuous bending mode of a Tesla valve shape, so that the effective heat dissipation area is multiplied in a limited space, airflow is induced to form high-strength vortex, and the thermal resistance boundary layer is completely broken, so that targeted cooling of key heat sources is realized, the risk of hardware frequency reduction caused by local overheating is eliminated from the root, and the stability of continuous full-load operation of the server is ensured.

The invention discloses an NPU-based edge computing video stream processing method and system. The method comprises the steps of video stream data acquisition and writing-in, zero-copy hardware preprocessing, model loading and asynchronous reasoning and result acquisition and post-processing. According to the method, a'control-calculation 'hardware-level decoupling architecture is constructed, and a special NPU is started to execute reasoning, so that the load and the power consumption of a CPU are greatly reduced, and the problems of frequency reduction and dead halt of a system caused by overheating of the CPU are thoroughly solved. A full-link zero-copy data channel based on DMA and RGA hardware is established, so that the video stream processing delay is remarkably reduced, and stable real-time analysis under a high frame rate is realized. By adopting the operator fusion and INT8 hybrid quantization technology, the calculation and memory access efficiency of the model on the NPU is multiplied, and higher energy efficiency ratio and throughput are obtained while the precision is ensured. Finally, the edge equipment can stably run at low temperature for a long time in a closed environment without fan heat dissipation.

This invention discloses an overclocking simulation calculation method for heat dissipation modules, applied to the optimal prediction of overclocking / downclocking factors and times for heat pipe and other heat dissipation modules. New-generation AIPC chips, in order to achieve higher computing performance, have built-in powerful overclocking capabilities. However, when paired with existing heat pipe heat dissipation modules, an optimal combination of overclocking factor and time is needed to maximize the computing performance of the built-in overclocking function. Higher overclocking factors result in better performance, but the overclocking time must be shorter; the frequency must be reduced before reaching the chip's temperature limit to avoid exceeding the chip's temperature range. Therefore, by simulating the combination of parameters such as overclocking factor, overclocking time, downclocking factor, and downclocking time using equations, without exceeding the chip's temperature limits, development costs can be significantly reduced.

The application discloses a segmented soft-start control method for forward charging of a bidirectional CLLC resonant converter, relates to the technical field of power electronic converter control, and is realized based on an on-board charger (OBC) system, wherein the OBC system comprises a front-stage totem pole PFC rectifier circuit, a CLLC charging and discharging circuit and an auxiliary power supply circuit, the PFC output voltage is used as the CLLC primary bus voltage, the CLLC secondary side output is used for battery charging, and the system is controlled by an external BMS or a host computer. According to the method, a dynamic parameter setting algorithm based on model prediction is adopted, the minimum constant current point under different starting conditions is automatically adjusted, the stability of soft starting under various conditions is realized, the smooth transition of the control mode is ensured in view of the stage switching oscillation problem, the problems of gain mutation at the soft start end time of the initial fixed slope frequency reduction strategy and long soft start time are solved, the gain of the whole soft start process is closer to the gain curve of the converter, and therefore the resonant cavity peak current is further reduced.

The invention relates to a network construction type converter thermal control method considering low harmonic waves and junction temperature limitation, which belongs to the field of power electronic intelligent control, and comprises the following steps: locking a DPWM modulation mode of an optimal clamping interval under an overload condition, and carrying out coupling design with switching frequency control; switching frequency is scanned through off-line simulation, data of device peak junction temperature and grid-connected current changing along with the switching frequency are obtained respectively, and the data are solidified into a lookup table capable of being called by a controller; during operation, a feasible switching frequency interval is screened according to junction temperature and double constraints, a recommended switching frequency interval is given, and an optimal frequency reduction working point is selected according to a provided selection function in the frequency interval meeting requirements, so that dynamic compromise between thermal safety and system performance during overload is realized. According to the method, the optimal operation frequency point is given under the condition of fully considering the DPWM and frequency reduction coupling effect, so that the safe and compliant operation of the converter under the overload working condition is realized.

This invention discloses a CPU dynamic frequency adjustment method based on multi-level load detection, comprising the following steps: S1, creating three load detection tasks and setting their priorities among different priority levels of real-time operating system tasks; S2, setting different decision cycles for the business characteristics of tasks with different priorities; S3, obtaining the idle level of the corresponding priority task group by detecting whether the three load detection tasks can be scheduled for execution; S4, adjusting the CPU frequency according to the idle level of different priority task groups. By setting load detection tasks among different priority levels of tasks, fine-grained monitoring is achieved, ensuring timely frequency increase for high-priority tasks when resources are insufficient to guarantee real-time performance. The differentiated decision cycle enables millisecond-level rapid response to sudden business events, and the precise perception of load conditions at each level achieves optimal frequency reduction to maximize energy saving, thus achieving a balance between real-time performance assurance and energy efficiency optimization.

The invention relates to the technical field of power module control, in particular to a self-adaptive junction temperature control power module control method, which comprises the following steps: collecting a junction temperature instantaneous value of a to-be-predicted module, and predicting a residual life decay rate by adopting a long-short term memory model; the switching frequency of the to-be-predicted module is reduced according to the junction temperature change rate, and the junction temperature change rate is collected and generated again; and performing secondary optimization on the switching frequency according to the newly generated junction temperature change rate. In order to solve the problems that a power module control method in the prior art only performs linear control on temperature rise and is poor in life loss optimization, in the scheme, a secondary optimization process is designed for the influence degree of junction temperature fluctuation on the residual life of the power module, firstly, the severe temperature rise is intervened through a simple junction temperature change rate, and then the residual life of the power module is optimized; the further aggravation of temperature rise fluctuation is avoided through a frequency reduction mode, and secondary optimization is carried out on the condition of residual life loss in a long term predicted based on the junction temperature change rate, so that a relatively good control effect on the power module is realized.

The invention provides a performance parameter adjusting method and device, a chip, electronic equipment and a medium, and relates to the technical field of communication. Comprising the steps that based on indication information of network equipment, a target gear interval is determined in multiple sets of candidate gear information of performance parameters of a terminal, the performance parameters comprise frequencies and voltages, and each set of candidate gear information corresponds to a set of voltages and frequencies for a central processing unit and / or at least one hardening accelerator of the terminal; determining a target gear in the target gear interval based on the running state information of the terminal under the current working load; and respectively adjusting performance parameters of the central processing unit and / or the at least one hardening accelerator based on the target gear. According to the method provided by the invention, invalid power consumption can be greatly reduced, and the battery life is effectively prolonged; through adjustment of the determined target gear, severe fluctuation of performance is avoided, jamming caused by instantaneous high load and subsequent temperature control frequency reduction is reduced, and continuous and stable user experience is guaranteed.

The apparatus includes a clock skew calibration circuit configured to be coupled to the multi-phase clock generator via a plurality of delay lines, wherein the first clock skew calibration unit comprises: a frequency multiplier configured to receive a plurality of multi-phase clock signals and to generate a clock signal based on the plurality of multi-phase clock signals; a frequency divider configured to receive the clock signals and to generate a reduced frequency signal based on the clock signals; and a delay line control circuit configured to compare a duty cycle of the reduced frequency signal with a predetermined duty cycle and to generate a first control signal to adjust the skew of the first multi-phase clock signals by adjusting a first delay applied to the first multi-phase clock signals until a calibrated signal of the first multi-phase clock signals is achieved.

The disclosure provides a voltage drop control method, which comprises the following steps: obtaining a to-be-executed instruction path; determining whether the to-be-executed instruction path is a marked instruction path; and enabling a preset current limiting strategy to execute the to-be-executed instruction path in the case that the to-be-executed instruction path is the marked instruction path, wherein the current limiting strategy is used to adjust voltage before triggering the voltage drop. The embodiment of the application can suppress voltage drop in advance by suppressing control voltage before the execution of the to-be-executed instruction path, suppress voltage drop with a small performance cost, reduce the triggering probability of frequency reduction for suppressing voltage drop, and further reduce the power consumption gain of the operating voltage of the CPU.

The invention discloses a frequency source rapid taming locking method and system and a storage medium, and belongs to the technical field of time frequency. The method comprises the following steps: S1, reducing the frequency of an initial reference signal and a measured signal to a target frequency through a frequency divider, and outputting the target frequency to a phase discriminator; s2, the MCU module reads the time difference value measured by the phase discriminator in an SPI mode; s3, calculating relative frequency deviation according to the time difference value; s4, after the relative frequency deviation is obtained through calculation, a frequency control word is adjusted according to the parameters of the local time source to be used for the local time source, and the frequency of the local time source is locked to the frequency of the reference source; s5, the MCU module calculates a phase deviation according to the time difference value and writes the phase deviation into the phase modulator, and finally outputs a preset frequency signal of which the frequency and the phase are synchronized to the reference source; and S6, setting the number of times of repeating the steps S2 to S5 according to requirements, and enabling the signal output by the local time source to be close to the signal of the reference source, thereby finishing taming locking of the local time source. The taming time can be shortened, and the purpose of fast taming and locking is achieved.

The application claims a pipeline ADC variable step size LMS calibration system based on inverse hyperbolic sine function, comprising a high-speed pipeline ADC module to be calibrated, a low-speed system clock module, a low-speed high-precision sigma-delta ADC, a variable step size adaptive filter, a digital frequency reducer and a subtractor. On the basis of the traditional LMS algorithm, the inverse hyperbolic sine function arcsinh x is introduced, the improved step size factor updating mode, and the step size factor E(n) is updated according to the square sum of the error and the square difference of the input signal. Accordingly, the mathematical model of the step size, the input signal and the error is established as mu(n)=p·arcsinh(beta·E(n)), the step size is updated in real time according to the error signal size, and the minimum error and the corresponding filter weight and output result are saved at each time of updating the filter weight. In this way, the optimal filter weight and the corresponding output result can be obtained after the algorithm is run. The algorithm has the advantages of high calibration accuracy, fast convergence speed and the like.

The present application belongs to the field of heat pump air conditioner, and relates to a heat pump double-system defrosting control method and device, computer equipment and storage medium. The method comprises: collecting real-time operation parameters and establishing a heating operation benchmark; when the first system meets the comprehensive defrosting condition, locking the real-time environment temperature value and sending a frequency locking signal to the second system; the first system switches to the defrosting mode at a reduced frequency, and the second system freezes the current operation frequency after receiving the frequency locking signal; during the defrosting of the first system, the second system maintains the frozen frequency operation and continuously monitors its own operation parameters; after the first system switches back to the heating mode, the frequency locking state and the environment temperature locking state of the second system are maintained for a preset time; the frequency locking and the environment temperature locking are released in stages, and a defrosting shielding timer is started for the system that completes defrosting. The heat loss and the waste of electric energy caused by frost-free defrosting are avoided; when facing complex and variable actual working conditions, stability and reliability can be maintained.

The application relates to a compressor variable frequency control method based on load self-adaption and electronic equipment, wherein the dynamic frequency of the platform is decided by the initial ambient temperature and the initial water outlet temperature difference, the starting strategy is accurately matched with the real-time load, and the initial operation state is improved; the current water inlet temperature change rate and the current water outlet temperature difference are monitored in the platform operation stage, it is determined whether the PID control after the platform ends is performed after the working condition is pre-judged as the minimum load fast temperature-tending state, the shutdown problem caused by the PID response delay is effectively solved, the control method significantly reduces the compressor start-stop times under small load, temperature control is more stable, user experience is improved, the equipment life is prolonged, and the part load energy efficiency ratio of the system is improved.

The invention provides a read-write control system and method based on a single clock domain SRAM (Static Random Access Memory). The read-write control system comprises an SRAM control module, an odd SRAM module, an even SRAM module, an odd-even data selection module and an FIFO (First In First Out) module. Comprising the following steps: setting an SRAM read-write mode and an SRAM clock frequency division factor n; and based on the SRAM read-write mode and the SRAM clock frequency division factor n, using a single port to read and write the SRAM. The single-clock-domain SRAM has the advantages that the single-clock-domain SRAM is smaller in use area, lower in power consumption and lower in cost, the odd SRAM module and the even SRAM module are designed, and the function of reading and writing at the same time is achieved; the SRAM control module is designed to realize special SRAM control, so that the memory can simultaneously read and write in a first-in and second-out mode; an odd-even selection module and a matched FIFO (First In First Out) are designed, so that the memory can carry out 1 / n-time frequency reduction on a data stream; and the complexity caused by multiple clock domains is reduced.

The invention relates to a design method of a portable high-performance LRM calculation module, and belongs to the field of high-performance calculation. Hardware of the LRM calculation module is provided with a main control system, an input and output system, a power supply system, a storage system and other systems. Based on a domestic single-path Feiteng S5000C / 16 core processor, a main control system of an LRM calculation module is designed, and a high-speed PCIE channel is provided for a peripheral chip; the module power is reduced under the condition of ensuring stable operation of an application program, and the adaptive capacity under multiple scenes is improved by adopting frequency reduction, voltage reduction and check-off technologies according to different use requirements of the module under different working scenes; the strength design, electromagnetic shielding, heat dissipation and corrosion protection factors of the module are comprehensively considered, and the lightweight and portable design of the module is realized. By optimizing a system hardware architecture platform, efficient operation of the module is realized, and the system has the characteristics of expandability, low delay and high reliability.

This invention belongs to the field of collaborative heat dissipation technology. It provides a dynamic scheduling method and system for collaborative heat dissipation of CPUs and GPUs, comprising: real-time monitoring of the operating status parameters of the CPU and GPU, and based on these parameters, predicting the thermal load change trends of the CPU and GPU within a preset future time period; dynamically setting the optimal energy-efficiency operating points for the CPU and GPU respectively based on the thermal load change trends and in conjunction with their respective chip energy efficiency models; wherein, the optimal energy-efficiency operating point is set under predicted thermal and power constraints. Through prediction-driven dynamic optimal energy-efficiency operating point setting and an anti-throttling spiral strategy, the power distribution between computing units and cooling fans can be intelligently coordinated under total power constraints, avoiding a vicious cycle of performance degradation and increased high temperatures caused by fan speed increases crowding out computing resources, thus solving the common problems of high noise and low performance in collaborative heat dissipation.

1. Name of the product in this design: Intelligent graphical user interface for extracting economic data for electronic devices. 2. Purpose of this design: An electronic device. 3. The key design features of this product are the content displayed in the graphical user interface. 4. The image or photograph that best illustrates the design's key features: the front view. 5. The design for which protection is sought includes color. 6. The carrier uses a conventional design, omitting the rear view, top view, bottom view, left view, and right view. 7. Purpose of the graphical user interface: The graphical user interface is the functional interface of the macroeconomic module's economic database, used for setting and applying intelligent extraction rules for economic data. In the main view, select the "Priority Upgrade" option in the pop-up window to enter the interface change state diagram 1. In the interface change state diagram 1, click the drop-down box to the right of "Variable Frequency Calculation" to enter the interface change state diagram 2. In the interface change state diagram 2, select the "Prioritize Frequency Reduction" option to enter the interface change state diagram 3. In the interface change state diagram 3, click the drop-down box to the right of "Variable Frequency Calculation" to enter the interface change state diagram 4. In the interface change state diagram 4, click the "Unit Conversion" button to enter the interface change state diagram 5. In the interface change state diagram 5, click the "Currency Conversion" button to enter the interface change state diagram 6. In the interface change state diagram 6, select the "Custom Currency Priority" option to enter the interface change state diagram 7. In the interface change state diagram 7, click on the currency listed under "Custom Currency Priority" to enter the interface change state diagram 8. In the interface change state diagram 8, click the "Supplement Interval" button to enter the interface change state diagram 9. In the interface change state diagram 9, enter information in the search bar in the upper left corner and click the rightmost button in the search bar to enter the interface change state diagram 10. In the interface change state diagram 10, double-click the item found in the left-hand list to enter the interface change state diagram 11, and add the item to the indicator list on the right. In the interface change state diagram 11, click the "Smart Frequency Selection" button in the table on the right to enter the interface change state diagram 12. In the interface change state diagram 12, click the "Priority Upgrade" button in the pop-up list to enter the interface change state diagram 13. In the interface change state diagram 13, click the "Prioritize Frequency Reduction" button in the pop-up list to enter the interface change state diagram 14. In the interface change state diagram 14, click the "Smart Unit" button in the table on the right to enter the interface change state diagram 15. In the interface change state diagram 15, click the "Unit Conversion" button in the pop-up list to enter the interface change state diagram 16. In the interface change state diagram 16, click the "Currency Conversion" button in the pop-up list to enter the interface change state diagram 17. In the interface change state diagram 17, click the "Extract Data" button above the table on the right to enter the interface change state diagram 18. 8. Other situations requiring explanation: The human avatar in the view is the image of the software's virtual assistant and is not a real person's portrait or a variable content screen.

The application belongs to the technical field of software development equipment, and discloses a debugging device for computer software technology development. The debugging device for computer software technology development comprises a bottom shell and a top cover, the inner bottom wall of the bottom shell is movably connected with the middle portion of the lower surface of the top cover through an elastic member, the inner side wall of the bottom shell is provided with a plurality of device installation modules for the installation of electronic devices, and the inner bottom wall of the bottom shell is provided with air outlet holes for air circulation. The debugging device for computer software technology development can quickly remove a large amount of heat generated during the operation of the device through the cooperative operation of the ventilation mechanism and the heat exchange assembly, effectively reduces the working temperature of the PCB circuit board and the electronic device, avoids the hardware frequency reduction and operation lag caused by high temperature, ensures the stable operation of the emulator during the software debugging process, and solves the problems of low heat dissipation efficiency and easy overheating of the hardware of the traditional debugging device.

The invention relates to the technical field of semiconductor thermal management, and discloses an edge computing task scheduling system of a diamond-based semiconductor device, which comprises an instruction preprocessing module, a thermal sensing control module and a scheduling execution module. The instruction preprocessing module reorganizes the instruction sequence into micro-slices and marks the micro-slices as a high-power burst type or a low-power gap-filling type. The thermal sensing control module calculates a predicted junction temperature based on the real-time voltage and current using a transient thermal impedance model. The scheduling execution module regulates and controls hardware according to a comparison result of the junction temperature and a safety threshold; when the junction temperature is safe, burst slicing is executed; when the junction temperature reaches the limit, the clock frequency and the voltage are kept unchanged, and a gap-filling slice is inserted and executed. According to the invention, the rapid thermal relaxation characteristic of the diamond substrate is utilized, active cooling of the device is realized through instruction flow gap filling on the premise of no frequency reduction and no voltage regulation, the switching overhead of the traditional frequency and voltage regulation technology is avoided, and the energy efficiency ratio and the thermal stability of the system are improved.

The application relates to the technical field of data processing, and particularly provides a memory data processing method and device for an operating system under strong electromagnetic interference, wherein the ripple voltage of a power management chip, the bus eye width of a memory controller bus and the memory temperature of DRAM are periodically polled; in each polling cycle, the ripple voltage, the bus eye width and the memory temperature are compared with a preset threshold set, and if any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are synchronously triggered; through parameter polling and hierarchical error repair, active protection of memory data under strong electromagnetic interference is realized. By adopting an adaptive polling cycle, the power ripple, the bus eye width and the DRAM temperature are collected in real time, error repair and memory frequency reduction are synchronously started, interference diffusion is blocked, the success rate of atomic page replacement repair is improved, the system stability is improved under a strong electromagnetic environment, and the problem of guaranteeing the integrity of memory data under extreme interference is effectively solved.

The invention provides a large-scale metering device data synchronization method based on a hierarchical synchronization technology, and the method comprises the steps: collecting synchronization signal response difference data among multiple layers of equipment in a hierarchical synchronization architecture, obtaining a distribution parameter for introducing microsecond delay, and comprehensively determining a preliminary influence range of a delay amplification mechanism under the increase of a communication load; according to the determined influence range of the delay amplification mechanism, a real-time monitoring method is adopted to analyze dynamic changes of synchronization request density and load interaction, and an offset value of the acquisition moment dislocation in a power frequency signal period is obtained; according to the obtained adjustment coefficient, processing a data flow of an auxiliary monitoring node in the hierarchical synchronization architecture by adopting a frequency reduction operation, and determining a synchronization precision index after the network pressure is reduced; and through the determined synchronization precision index, obtaining a verification log of the fault diagnosis reliability under physical alignment implementation, and judging whether there is a residual dislocation residual error in the alignment data set of the synchronization signal and power frequency signal periods among the multiple layers of equipment.