Method for reducing power consumption of electric energy metering chip

Abstract

The invention provides a method for reducing power consumption of an electric energy metering chip. The electric energy metering chip is provided with two clock domains, wherein a CPU (Central Processing Unit) of the electric energy metering chip is located at a clock region I and a metering circuit is located at a clock region II; the clock region I selectively utilizes a low-frequency clock and high-frequency clock; for the clock region I, the movement can be stopped to keep a constant electrical level; the clock region II selectively utilizes a low-frequency clock, a frequency-reducing clock and a high-frequency clock and for the clock region II, the movement can be stopped to keep the constant electrical level; and the electric energy metering chip can be selectively powered by a battery or a power line. According to the method disclosed by the invention, a plurality of clock combinations are arranged for a chip of an electric energy metering system and the switching of the clock combinations is carried out according to current power supply states of the chip of the system and a resetting generation source is dormant or awakened, so that the method is good for reducing the power consumption of the chip of the electric energy metering system.

Description

technical field [0001] The present invention relates to a method for reducing power consumption, in particular to a method applied in an electric energy metering chip to reduce the power consumption of the electric energy metering chip. Background technique [0002] In CMOS circuits, there are three sources of power consumption, namely . where P total is the total power dissipation of a CMOS circuit, P switching is the switching power consumption, which depends on the charge and discharge of the load capacitor; P leakage is the leakage power consumption. The most important power consumption in current chips is switching power consumption, but with the application of low threshold voltage technology in low power consumption design, short-circuit power consumption and leakage power consumption will become more and more important. [0003] where switching power consumption , VDD is the supply voltage; f clk is the clock frequency; if a circuit contains n nodes, a i is...

AI Technical Summary

Problems solved by technology

[0004] Short-circuit power consumption occurs at the moment of signal inversion. When the value of the input signal is between |Vth| and VDD-|Vtp|, PMOS and NMOS are turned on at the same time, resulting in a short-circuit current from VDD to GND

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