9 results about "Synchronous serial communication" patented technology

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes: a host configured to provide a clock signal; and a plurality of cascaded slave machines, each slave machine comprises a first serial interface and a second serial interface, the first slave machine is coupled to the host machine through the first serial interface, for adjacent slave machines, the second serial interface of the upstream slave machine is coupled with the first serial interface of the downstream slave machine, and the second serial interface of the downstream slave machine is coupled with the first serial interface of the downstream slave machine. Each slave synchronously receives a clock signal from the host through the first serial interface and the second serial interface. According to the synchronous serial communication system, the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of chip selection signals provided by the SPI host, the communication speed is not limited by the farthest distance slave, the communication speed is not limited by the number of the slaves, the communication speed can be increased, and the communication efficiency is improved. The communication efficiency is improved.

The present application relates to the field of communication technology, especially a method for compensating delay of synchronous serial communication, a compensated clock is generated in a host, the compensated clock is clk_compensation, the starting time of the compensated clock clk_compensation is the same as the edge time of the starting bit of received data, so the data sent by a slave is received by using the compensated clock clk_compensation, without calculating the specific time of line delay, the data sent by the slave can be accurately received; and since the communication is compensated in real time each time, even if the same host product uses different baud rates at different time, the data can be correctly read.The present application is applicable to different products of synchronous serial communication, has strong compatibility, and can greatly improve the speed of synchronous serial communication and the physical line length.

The invention discloses a synchronous serial communication system and method, and relates to the technical field of communication. The system comprises a master device and a slave device, the master device and the slave device are connected through a clock signal line and a data signal line, and the data signal line is connected with a pull-up resistor; the data frame of the write command sent by the master device to the slave device comprises a start bit, a read-write command bit, an address field, a first parity check bit, a write data field, a second parity check bit and an end bit; a data frame of a read command sent by the master device to the slave device comprises a start bit, a read-write command bit, an address field, a first parity check bit and an end bit; the data signal line is at a low level when at the start bit, and the data signal line is at a high level when at the end bit. The method can improve the communication speed and reduce the cost.

The application provides an error detection method, a detection system, equipment and a medium for synchronous serial communication. The error detection method for synchronous serial communication stores received synchronous serial data in a shift register in bits to form first data. Valid data of the first data is extracted and stored in a cache module. When the first data has a data error, the state of an error type identifier corresponding to each type of data error in the original frame header content is switched from a first state to a second state, first frame header data is obtained, and the first frame header data is sent to a receiving end. After receiving the data frame, the receiving end determines which error type identifier state is in the second state to obtain the error type of the error data frame, so that the receiving end can take corresponding measures according to the error type. The method provided by the application enables the receiving end to identify error data frames and obtain error types at the same time, thereby improving the reliability of the receiving end.

The invention discloses a linear motor multi-frequency-converter synchronous serial communication bus system and a synchronous control method, and belongs to the technical field of motor control. The bus adopts a master-slave type half-duplex synchronous serial communication architecture and comprises a master controller and at least one slave controller, high-speed parallel-serial data conversion is realized between the master controller and the slave controller through a serializer and a deserializer, and communication is performed through an optical module and an optical fiber, so that the complicated design of an FPGA (Field Programmable Gate Array) which is necessary in a traditional scheme is avoided. The synchronous control method is realized based on the bus, the main controller sends fixed data frames in each PWM control period, the slave controllers receive clock signals according to the deserializer to generate synchronous pulses after receiving the fixed data frames, and each slave PWM timer is reset by the aid of the pulses, so that PWM output phases of all the slave controllers are strictly synchronized, and the synchronous control is realized. And high-frequency harmonic interference generated by asynchronous operation of multiple frequency converters is effectively suppressed.

A synchronous serial communication controller, a synchronous serial communication peripheral component, and a computer-implemented method enabling synchronous serial communication between the synchronous serial communication controller and the synchronous serial communication peripheral component are provided. The example synchronous serial communication controller includes a serial communication interface, configured with a clock logic wire, a data output logic wire, a data input logic wire, and a shared select line logic wire. The shared select line logic wire is electrically connected to a plurality of peripheral components. A selected peripheral component of the plurality of peripheral components is indicated by chip identification data transmitted on the data output logic wire.

This application discloses a loopback self-test method, apparatus, system, electronic device, and medium, belonging to the field of communication protocol testing technology. The method includes: determining whether a target chip containing a synchronous serial communication interface has an external slave device; when the target chip does not have an external slave device, triggering the loopback test mode of the target chip; in the loopback test mode, configuring the synchronous serial communication interface to master mode and performing a loopback self-test. Through the embodiments of this application, the target chip can perform loopback testing without relying on external devices, thereby reducing testing complexity and costs.

An apparatus, such as a system-on-a-chip (SoC), includes a first processing unit configured to fetch a first subset of firmware from a first memory to a second memory in response to the apparatus being powered up. The apparatus also includes a second processing unit configured to execute the first subset of the firmware from the second memory. The first processing unit is configured to fetch a second subset of the firmware from the first memory to the second memory concurrently with the second processing unit executing the first subset. In some cases, the firmware includes Basic Input / Output System (BIOS) firmware or unified extensible firmware interface (UEFI) firmware. In some cases, the first memory is a nonvolatile flash memory that operates according to a serial peripheral interface (SPI) protocol for synchronous serial communication and apparatus includes an SPI interface.

The invention provides electronic equipment, an interrupt processing method and a storage medium, and relates to the technical field of computers. The electronic device runs based on a processor platform of a reduced instruction set, the electronic device comprises an embedded controller, a processor, a first target bus, a second target bus and at least one sub-device, the processor is based on the reduced instruction set, and the first target bus and the second target bus are both I2C buses. The I2C bus is a bidirectional two-wire system synchronous serial communication bus; the embedded controller is connected with the processor through a first target bus, so that the embedded controller communicates with the processor; the embedded controller is connected with each sub-device through a second target bus, so that the embedded controller communicates with each sub-device; the embedded controller and the sub-equipment are respectively configured as I2C equipment in the ACPI configuration table, so that the embedded controller, the embedded controller driver and the sub-equipment driver can run on the ARM platform, and the development workload of the ARM platform is reduced.