Multi-chip serial communication system

Abstract

The invention discloses a multi-chip serial communication system. The multi-chip serial communication system is a multistage operation chip serial communication structure formed through connecting downlink data reception ends, downlink data transmission ends, uplink data reception ends, uplink data transmission ends, flow control reception ends and flow control transmission ends of a plurality ofoperation chips; and a control chip is connected with the 0-stage operation chip to form a serial communication system structure. Transmission of uplink data of the operation chips is coordinated through flow control signals of the flow control reception ends and the flow control transmission ends by utilizing designed downlink and uplink communication protocols. The system provided by the invention is low in line structure design difficulty, so that the production cost is lower; by means of uplink and downlink serial communication protocols, mutual interference between the uplink and downlinkcommunication data of each operation chip is eliminated, so that each operation chip and correctly receive and transmit the data; and meanwhile, two manners of broadcast and unicast are supported, sothat both efficiency and flexibility are considered.

Description

Technical field [0001] The invention relates to the field of chip wiring communication, in particular to a multi-chip serial communication system. Background technique [0002] A complex computing system with a huge amount of computing is often composed of a control chip and many computing chips, such as figure 1 As shown, in this system, the control chip is responsible for configuring computing chips and distributing computing tasks to each computing chip. Each computing chip is responsible for processing computing data and returning computing results to the control chip. It should be noted, figure 1 It is only an example, which does not include the connection relationship between the various computing chips and the connection relationship with the control chip, where the number of computing chips only represents multiple, and does not have the effect of limiting the number of computing chips. [0003] As the performance requirements of the computing system become higher and highe...

AI Technical Summary

Problems solved by technology

[0010] The disadvantage of this method is that the control chip and the computing chip share the communication path, the independence between the computing chips is affected, and there may be mutual interference during communication, which requires a reasonable and efficient communication mechanism to be constrained.

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