LDMOS transistor and manufacturing method thereof

Abstract

The invention discloses an LDMOS which comprises a P-type substrate, an N-type epitaxial layer, a P trap, a first N-type doping region, a groove, a first metal layer and a source-electrode metal layer. The P trap is located in the N-type doping region, the first N-type doping region is arranged in the P trap, and the groove penetrates through the first N-type doping region, the P trap and the N-type epitaxial layer until the P-type substrate. A first oxidation layer is arranged on the side wall of the groove. The groove is filled with first polycrystalline silicon of P-type doping. The upper surface of the first polycrystalline silicon is located inside the P trap and is lower than the first N-type doping region. The first metal layer covers the upper surface of the first polycrystalline silicon and covers the first N-type doping region. The source-electrode metal layer is located on the back face of the P-type substrate. The invention further discloses a manufacturing method of the LDMOS. A source electrode is led out from the back face of the substrate instead of being originally led out from the front face of the substrate, the design area of the original source electrode region on the front face is effectively reduced, the design width of a channel in a gate region is increased, and the on resistance is reduced.

Description

Technical field

[0001] The present invention relates to an LDMOS and a manufacturing method thereof, in particular to an LDMOS and a manufacturing method thereof with a source electrode drawn from the backside of a wafer and perfectly compatible with the existing CMOS process. Background technique

[0002] LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) has a fast switching speed and can meet high breakdown voltage applications. It can withstand higher power, higher operating frequency, and more than bipolar transistors. It is easily compatible with Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor, bipolar and complementary metal oxide semiconductor) integrated circuit technology and can form BCD (Bipolar CMOS DMOS, dual CMOS integrated circuit technology) circuit as its high-voltage unit and other advantages. Widely used, DCMOS circuits are widely used in drivers, high-frequency power amplifiers and other occasions.

[0003] LDNMOS (N-type LDMOS) manufactured us...

Examples

Embodiment 1

[0112] reference Figure 4 First, an N-type epitaxial layer 201 is formed on the surface of a P-type substrate 200 through an epitaxial process. Wherein, the P-type substrate 200 is a high-concentration doped outsourced original silicon wafer, the resistivity of the P-type substrate is 0.001 ohm·cm, the N-type epitaxial layer 201 is formed by an epitaxial process, and the N-type epitaxial layer 201 serves as the drain of the LDMOS, which will withstand higher source and drain voltages. In this embodiment, the N-type epitaxial layer has a resistivity of 0.3 ohm·cm and a thickness of 3 μm. The specific epitaxial growth process conditions are: silane thermal decomposition method is used for vapor phase epitaxy, the reactant is silane, the N-type dopant phosphine, the epitaxy temperature is 1100°C, and the time is 20 minutes. The epitaxial thickness is determined by the LDMOS operating voltage, that is, the source and drain voltages. The higher the voltage, the greater the thicknes...

Embodiment 2

[0138] The principle of embodiment 2 is the same as that of embodiment 1, and the main steps are also the same. The only difference is the selection of the following process parameters:

[0139] The resistivity of the P-type substrate is 0.01 ohm·cm, the resistivity of the N-type epitaxial layer is 1.0 ohm·cm, the thickness is 5 μm, and the epitaxial temperature for forming the N-type epitaxial layer is 1200° C. and the time is 40 minutes.

[0140] The thickness is first grown by thermal oxidation process Lining oxide layer, and then deposit silicon nitride by low pressure chemical vapor deposition process, where the thickness of silicon nitride is The thickness of the field oxide layer 207 grown by the thermal oxidation process is

[0141] The formation condition of the P-type doped region 202 is: the doping dose is 1e14cm -2 The boron ions are accelerated to 200 keV for P-type ion implantation to form a P-type doped region 202 in the N-type epitaxial layer.

[0142] The ion implan...

Embodiment 3

[0154] The principle of embodiment 3 is the same as that of embodiment 1, and the main steps are also the same. The only difference is the selection of the following process parameters:

[0155] The resistivity of the P-type substrate is 0.005 ohm·cm, the resistivity of the N-type epitaxial layer is 0.8 ohm·cm, the thickness is 7 μm, and the epitaxial temperature for forming the N-type epitaxial layer is 1150° C. and the time is 45 minutes.

[0156] The formation condition of the P-type doped region 202 is: the doping dose is 5e14cm -2 The boron ions are accelerated to 150 keV for P-type ion implantation to form a P-type doped region 202 in the N-type epitaxial layer.

[0157] The ion implantation conditions of arsenic ions are: energy: 50keV; doping dose: 5e16cm -2 .

[0158] The thermal propulsion conditions for forming the P trap are: the thermal propulsion temperature is 1050° C., the thermal propulsion time is 100 minutes, and the channel length L is 1.5 μm.

[0159] The thickness ...

Technical field

[0001] The present invention relates to an LDMOS and a manufacturing method thereof, in particular to an LDMOS and a manufacturing method thereof with a source electrode drawn from the backside of a wafer and perfectly compatible with the existing CMOS process. Background technique

[0002] LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) has a fast switching speed and can meet high breakdown voltage applications. It can withstand higher power, higher operating frequency, and more than bipolar transistors. It is easily compatible with Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor, bipolar and complementary metal oxide semiconductor) integrated circuit technology and can form BCD (Bipolar CMOS DMOS, dual CMOS integrated circuit technology) circuit as its high-voltage unit and other advantages. Widely used, DCMOS circuits are widely used in drivers, high-frequency power amplifiers and other occasions.

[0003] LDNMOS (N-type LDMOS) manufactured us...

Examples

Embodiment 1

[0112] reference Figure 4 First, an N-type epitaxial layer 201 is formed on the surface of a P-type substrate 200 through an epitaxial process. Wherein, the P-type substrate 200 is a high-concentration doped outsourced original silicon wafer, the resistivity of the P-type substrate is 0.001 ohm·cm, the N-type epitaxial layer 201 is formed by an epitaxial process, and the N-type epitaxial layer 201 serves as the drain of the LDMOS, which will withstand higher source and drain voltages. In this embodiment, the N-type epitaxial layer has a resistivity of 0.3 ohm·cm and a thickness of 3 μm. The specific epitaxial growth process conditions are: silane thermal decomposition method is used for vapor phase epitaxy, the reactant is silane, the N-type dopant phosphine, the epitaxy temperature is 1100°C, and the time is 20 minutes. The epitaxial thickness is determined by the LDMOS operating voltage, that is, the source and drain voltages. The higher the voltage, the greater the thicknes...

Embodiment 2

[0138] The principle of embodiment 2 is the same as that of embodiment 1, and the main steps are also the same. The only difference is the selection of the following process parameters:

[0139] The resistivity of the P-type substrate is 0.01 ohm·cm, the resistivity of the N-type epitaxial layer is 1.0 ohm·cm, the thickness is 5 μm, and the epitaxial temperature for forming the N-type epitaxial layer is 1200° C. and the time is 40 minutes.

[0140] The thickness is first grown by thermal oxidation process Lining oxide layer, and then deposit silicon nitride by low pressure chemical vapor deposition process, where the thickness of silicon nitride is The thickness of the field oxide layer 207 grown by the thermal oxidation process is

[0141] The formation condition of the P-type doped region 202 is: the doping dose is 1e14cm -2 The boron ions are accelerated to 200 keV for P-type ion implantation to form a P-type doped region 202 in the N-type epitaxial layer.

[0142] The ion implan...

Embodiment 3

[0154] The principle of embodiment 3 is the same as that of embodiment 1, and the main steps are also the same. The only difference is the selection of the following process parameters:

[0155] The resistivity of the P-type substrate is 0.005 ohm·cm, the resistivity of the N-type epitaxial layer is 0.8 ohm·cm, the thickness is 7 μm, and the epitaxial temperature for forming the N-type epitaxial layer is 1150° C. and the time is 45 minutes.

[0156] The formation condition of the P-type doped region 202 is: the doping dose is 5e14cm -2 The boron ions are accelerated to 150 keV for P-type ion implantation to form a P-type doped region 202 in the N-type epitaxial layer.

[0157] The ion implantation conditions of arsenic ions are: energy: 50keV; doping dose: 5e16cm -2 .

[0158] The thermal propulsion conditions for forming the P trap are: the thermal propulsion temperature is 1050° C., the thermal propulsion time is 100 minutes, and the channel length L is 1.5 μm.

[0159] The thickness ...

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