RET IGBT with self-bias PMOS and manufacturing method thereof
A self-biasing, split gate technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of device breakdown voltage degradation, increase device switching loss, and reduce device switching speed.
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Embodiment 1
[0052] An embodiment of a RET IGBT device with self-biased PMOS, as figure 2 As shown, it includes: back collector metal 1, P-type collector region 2, N-type field stop layer 3 and N-drift region 4 stacked sequentially from bottom to top, with a trench gate structure above the N-drift region 4 , the trench structure includes a gate dielectric layer 6, a gate electrode 7, and a dielectric layer 10 above the gate dielectric layer 6 and the gate electrode 7; it is characterized in that: a P-type buried layer 12 is provided above the N-drift region 4, . A split gate structure, the split gate structure includes a polycrystalline split gate electrode 15, a gate dielectric layer 14; the top of the P-type buried layer 12 has an N-type charge storage layer 13; the top of the N-type charge storage layer 13 has a P type base region 5; the upper part of the P-type base region 5 has an N+ emitter region 8 and a P+ contact region 9; Metal 11; the gate electrode 7 is connected to the N-drif...
Embodiment 2
[0054] An embodiment of a RET IGBT device with self-biased PMOS, as image 3 As shown, it includes: back collector metal 1, P-type collector region 2, N-type field stop layer 3 and N-drift region 4 stacked sequentially from bottom to top, with a trench gate structure above the N-drift region 4 , the trench structure includes a gate dielectric layer 6, a gate electrode 7, a dielectric layer 10 above the gate dielectric layer 6 and the gate electrode 7; it is characterized in that there is a P-type buried layer 12 above the N-drift region 4, separating Gate structure, the separated gate structure includes a polycrystalline separated gate electrode 15, a gate dielectric layer 14; the upper part of the P-type buried layer 12 has an N-type charge storage layer 13; the upper part of the N-type charge storage layer 13 has a P-type base Region 5; the upper part of the P-type base region 5 has an N+ emitter region 8 and a P+ contact region 9; the upper part of the dielectric layer 10, ...
Embodiment 3
[0056] An embodiment of a RET IGBT device with self-biased PMOS, as Figure 4 As shown, on the basis of Embodiment 1, a super junction structure composed of super junction N pillars 41 and super junction P pillars 42 is introduced into the drift region, and the junction depth of the super junction P pillars 42 is less than or equal to the junction depth of the super junction N pillars 41. deep, a separate gate electrode 71 is introduced below the gate electrode 71 , and the separate gate electrode 71 is short-circuited with the separate gate electrode 15 .
[0057] The introduction of the super junction structure further reduces the turn-on voltage drop of the device and increases the breakdown voltage of the device, and the introduction of the separated gate electrode 71 further reduces the Miller capacitance of the device.
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Abstract
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