15 results about "Switched capacitor integrator" patented technology

A system and method for measuring mutual inductance between adjacent first communication transmission line and second communication transmission line is disclosed. The system includes a mutual inductance measurement circuit that includes a coupling generator which biases the first communication transmission line with a current ramp signal; a sample and hold circuit which captures an induced voltage on the second communication transmission line using a switched capacitor storage element; a switched capacitor integrator configured to integrate the induced voltage onto an output voltage node; and a comparator configured to switch states once the switched capacitor integration has surpassed a reference trippoint.

Embodiments of interleaving switch cap integrator digital-to-analog converter (DAC) for low noise ramp generation while operating with low power supply voltage are described. In one embodiment, an image sensor includes: a plurality of pixels arranged in rows and columns of a pixel array; a bitline electrically coupled to an active pixel; and a switched capacitor current digital to analog converter (IDAC) coupled to the bitline. The IDAC includes a plurality of switch banks, where each switch bank is configured to receive a control signal for controlling opening and closing of switches of the switch bank. The control signals are offset in time. An integrator coupled to the plurality of switch banks. The integrator is configured for generating an output signal based on input signals received from the plurality of switch banks.

The invention provides an analog phase resolving circuit and method applied to a CMOS-TOF image sensor, the analog phase resolving circuit comprises a current source, an operational amplifier, an MOS tube M1, an MOS tube M2, an MOS tube M3, an MOS tube M4, an MOS tube M5, an MOS tube M6, an MOS tube M7, an MOS tube M8 and an adder, pixels of a four-tap structure are adopted, four paths of output signals with different phases are obtained through one-time exposure, the four paths of signals are subjected to differential processing through a switched capacitor integrator, and the output signals of different phases are obtained. And then the divider circuit performs division operation on the two differential signals, and the two differential signals are converted into digital codes through the analog-to-digital conversion circuit to be output. The method has the beneficial effects that division operation in a phase resolving process is converted from a digital domain to an analog domain and is carried out before analog-digital conversion in advance, so that high power consumption and area waste caused by a plurality of ADCs are avoided, and time and power consumption cost increase caused by the fact that a single ADC runs for a plurality of cycles is also avoided.

The invention discloses a strong PUF (Physical Unclonable Function) circuit for security protection of the Internet of Things, which comprises two TMR sensor arrays, two instrumentation amplifiers, two switched capacitor integrators and a comparator, and is characterized in that each TMR sensor array comprises a plurality of TMR sensor units, and the conduction number of the TMR sensor units in the two TMR sensor arrays is controlled through an excitation signal; two differential voltage signals are generated, two instrument amplifiers respectively carry out differential amplification on the two differential voltage signals to generate amplified voltage signals, two switched capacitor integrators respectively carry out sampling and accumulation on the amplified voltage signals to obtain sampled voltage signals, and the sampled voltage signals are output to a comparator. The comparator carries out voltage polarity judgment on the two sampling voltage signals to obtain a PUF response; the method has the advantages of high uniqueness and randomness, high stability, low bit error rate and high excitation-response pair number, and can meet the requirements of a high-reliability large-scale security authentication system.

The present invention discloses an operational amplifier structure using dynamic compensation in a ΣΔ modulator switched capacitor integrator, comprising a reference voltage input terminal, a feedback DAC capacitor, a sampling capacitor, a signal input terminal, an integrating capacitor, a fully differential folded cascode two-stage operational amplifier, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control switch. The structure has low power consumption.

The application discloses a kind of based on floating space dynamic amplifier and charge sharing's switched capacitor integrator, including the sampling module, integral module and charge sharing module connected in turn, wherein, sampling module is according to from the first enable signal, second enable signal, third enable signal and fourth enable signal from outside in sampling stage collection differential signal from outside, store differential signal, and in integral stage differential signal is output to integral module;Integral module is according to the first enable signal and fourth enable signal control operational amplifier in integral module in sampling stage charging and stop running, in integral stage differential signal is integrated;Charge sharing module is according to from the fifth enable signal from outside, in integral stage integral differential signal is stored and in next sampling stage output.The application is by designing operational amplifier, the circuit structure of charge sharing module and corresponding enable signal, reduce the overall power consumption of device and guarantee the precision of integrator.

The invention relates to an interleaved switched capacitor integrator (DAC) for low noise ramp generation with lower AVDD power supplies. Embodiments of an interleaved switched capacitor integrator digital-to-analog converter (DAC) for low noise ramp generation when operating with low supply voltages are described. In one embodiment, an image sensor includes: a plurality of pixels arranged in rows and columns of a pixel array; a bit line electrically coupled to the active pixel; and a switched capacitor current digital-to-analog converter (IDAC) coupled to the bit line. The IDAC includes a plurality of switch groups, wherein each switch group is configured to receive control signals for controlling opening and closing of switches of the switch group. The control signal is offset in time. An integrator is coupled to the plurality of switch groups. The integrator is configured to generate an output signal based on an input signal received from the plurality of switch groups.

The application discloses a modulator applied to a high-precision low-power analog-digital converter, comprising a signal input end, a signal output end, a digital-analog converter, and sequentially connected first analog adders, first analog integrators, second analog adders, second analog integrators, third analog adders and a first comparator for processing signals; wherein the first analog integrators and the second analog integrators are both switch capacitor integrators based on dynamic amplifiers, and the switch capacitor integrators comprise a second comparator for making the output common mode level of the dynamic amplifier reach a set value. The modulator provided by the application can realize higher precision with lower power consumption on the premise of higher chip yield.

The application provides a high-resolution two-step ADC for temperature sensing and an electronic device, and relates to the technical field of integrated circuits. A front-end buffer input end is coupled to a temperature-sensing front end; a switched capacitor integrator input end is coupled to an output end of the front-end buffer; a comparator input end is coupled to an output end of the switched capacitor integrator; a counter input end is coupled to an output end of the comparator; and a logic control unit input end is coupled to an output end of the comparator. The application proposes a structure of coarse quantization SDM+fine quantization SAR, without the need of additional high-speed counters, and the system power consumption and hardware complexity are reduced. By multiplexing the integration branch of the switched capacitor integrator, the comparator can not need to eliminate the offset voltage, further simplifying the comparator and the front-end buffer, and achieving the balance between high precision and low power consumption. The SDM can be high-speed running and has good noise performance for specific oversampling ratios, while realizing small chip integration size and low power consumption.

The invention provides an optical signal processing and converting system for optical fiber transmission. The optical signal processing and converting system comprises an optical fiber parameter extraction module, an A / D digital signal processing module, an FPGA module, a serial port module and a PC terminal. Wherein the optical fiber parameter extraction module provides a reference voltage Vref through a reference voltage circuit; in the optical signal acquisition channel, a high-power infrared light source provides optical excitation, an inclined grating losslessly separates target wavelength signals, a high-temperature stable gallium arsenide avalanche photodiode efficiently converts weak optical signals, and a high-sensitivity wide-spectrum photoelectric detector realizes photoelectric conversion. The photoelectric conversion interface circuit adopts a two-stage operational amplifier to dynamically adjust pre-amplification and buffer output so as to realize stable photoelectric signal extraction and reliable electric signal generation in a high-temperature environment; the A / D digital signal processing module adopts an open-loop source follower switched capacitor integrating circuit to be combined with a multi-bit quantizer and a data weighted average (DWA) feedback algorithm to realize analog-to-digital conversion with low noise and high dynamic range; the FPGA module improves the data throughput rate and the system synchronization precision through a parallel FIR architecture and dynamic serial port time sequence control; the PC end completes remote interaction and real-time data analysis through upper computer software. According to the system, through noise shaping, dynamic feedback adjustment and signal chain design, power consumption and harmonic distortion are reduced while high-precision conversion from an optical signal to a digital signal is achieved.

The invention relates to a parallel switch capacitor integrator insensitive to parasitic capacitance, which realizes high-precision signal integration processing through four steps: firstly, controlling switch logic by using a two-phase non-overlapping clock, ensuring that control signals are not overlapped, and reducing charging injection and clock feed-through; secondly, a resistor in the continuous time integrator is replaced by a switched capacitor simulation resistor, and current flow is simulated by utilizing a periodic charging and discharging process so as to control charge quantity transfer; then, a virtual switch is introduced to compensate the influence of charge injection, and the circuit performance is improved. And finally, a shunt capacitor integrator circuit is constructed, and the shunt capacitor integrator circuit is insensitive to parasitic capacitance through a specific circuit layout, so that high precision and linearity of an integrator are ensured.

The invention belongs to the technical field of integrated circuits. The invention provides a high gain floating inverting amplifier for a switched capacitor integrator. Embodiments of the present disclosure include circuit structures of a main amplifier and an auxiliary amplifier of a high gain floating inverting amplifier, and timing design. According to the high-gain floating inverting amplifier, two same auxiliary amplifiers are adopted to replace fixed bias voltage in a conventional sleeve type floating inverting amplifier circuit, and the gain of the sleeve type floating inverting amplifier is improved. According to the high-gain floating inverting amplifier, all floating nodes of the main amplifier and the auxiliary amplifier in the high-gain floating inverting amplifier are reset in the sampling stage, and the linearity of a switched capacitor integrator using the high-gain floating inverting amplifier as a core amplifier can be remarkably improved.

The application discloses a switched capacitor integrator, comprising a sampling capacitor, a dynamic amplifier, an integration capacitor and a common-mode feedback module; one end of the sampling capacitor receives an input signal through a switch assembly, and the other end of the sampling capacitor is connected with an input end of the dynamic amplifier and one end of the integration capacitor through the switch assembly; the other end of the integration capacitor is connected with an output end of the dynamic amplifier and one end of the common-mode feedback module; the other end of the common-mode feedback module is connected with a cascade output stage of the dynamic amplifier; the dynamic amplifier is used for amplifying a voltage signal collected by the sampling capacitor and outputting a common-mode voltage; the common-mode feedback module is used for generating a reference voltage and calibrating the common-mode voltage; and the integration capacitor is used for integrating operation on charges accumulated by the sampling capacitor and outputting a voltage signal proportional to the input signal.

The application discloses a kind of strong PUF circuits for Internet of Things security protection, including two TMR sensor arrays, two instrument amplifiers, two switched capacitor integrators and a comparator, TMR sensor array includes multiple TMR sensor units, the number of TMR sensor units in two TMR sensor arrays is controlled to be turned on by excitation signal, so that it generates differential voltage signal, two instrument amplifiers differentially amplify two differential voltage signals respectively, generate amplified voltage signal, two switched capacitor integrators are sampled and accumulated to amplified voltage signal respectively, and sample voltage signal is output to comparator, comparator carries out voltage polarity decision to two sample voltage signals, and obtains PUF response;The advantages are that it has higher uniqueness and randomness, and also has higher stability, lower bit error rate and higher excitation-response pair number, can meet the demand of high reliability large-scale security authentication system.