Strong puf circuit for iot security

Abstract

The application discloses a kind of strong PUF circuits for Internet of Things security protection, including two TMR sensor arrays, two instrument amplifiers, two switched capacitor integrators and a comparator, TMR sensor array includes multiple TMR sensor units, the number of TMR sensor units in two TMR sensor arrays is controlled to be turned on by excitation signal, so that it generates differential voltage signal, two instrument amplifiers differentially amplify two differential voltage signals respectively, generate amplified voltage signal, two switched capacitor integrators are sampled and accumulated to amplified voltage signal respectively, and sample voltage signal is output to comparator, comparator carries out voltage polarity decision to two sample voltage signals, and obtains PUF response;The advantages are that it has higher uniqueness and randomness, and also has higher stability, lower bit error rate and higher excitation-response pair number, can meet the demand of high reliability large-scale security authentication system.

Description

Technical Field

[0001] This invention relates to a strong PUF (Power Placement Function), and more particularly to a strong PUF circuit for Internet of Things (IoT) security protection. Background Technology

[0002] With the rapid development of the Internet of Things and smart terminals, the issues of identity authentication and data security of hardware devices are becoming increasingly prominent. Traditional encryption methods that rely on stored keys are vulnerable to physical attacks and cannot meet the security requirements of low-power, lightweight terminal devices.

[0003] Physically unclonable functions (PUFs) leverage the randomness inherent in device manufacturing to generate unique and uncopyable hardware fingerprints, thus becoming a crucial means of achieving hardware-level security. While existing silicon-based PUFs (such as arbiter PUFs, ring oscillator PUFs, and SRAM PUFs) are structurally mature, they generally suffer from high power consumption, large area, and sensitivity to voltage and temperature, leading to poor output response stability and high bit error rates. To address these shortcomings, researchers have begun exploring PUF designs based on the inherent randomness of sensors, aiming to improve stability and reliability while maintaining randomness.

[0004] For example, "X. Li, P. Wang, G. Li, L. Ni and Y. Zhang, "Design ofInterface Circuits and Lightweight PUF for TMR Sensors," in IEEE Sensors Journal A lightweight push-form element (PUF) based on a tunnel magnetoresistive sensor was proposed in "Journal of [Journal Name], Vol. 23, No. 11, pp. 11754-11761, June 2023". This PUF generates a PUF response by utilizing the resistance mismatch during the fabrication process of the TMR device and improves readout accuracy by using front-end modulation and a Σ-Δ modulator. However, the number of excitation-response pairs (CRPs) in this PUF is limited, making it a weak PUF. Its output is still susceptible to temperature drift and low-frequency 1 / f noise, and it exhibits significant jitter under repetitive excitation conditions, resulting in insufficient stability and a high bit error rate.

[0005] For another example, the document "X. Zhang, Z. Ji, X. Li, P. Wang, Y. Zheng and S. Wang, "Design of Gas Sensors-Based PUF for Internet of Things Security," in IEEE Sensors JournalThe paper "[Article Title], vol. 25, no. 7, pp. 11307-11313, April 2025" proposes a scheme for a gas sensor PUF that utilizes the perturbation of TiO2–ZnO nanofibers as a random source and combines median filtering and a multi-bit balancing algorithm to generate the PUF response. This scheme exhibits approximately 49.6% uniqueness and 98% randomness, demonstrating good uniqueness and randomness. However, due to the high sensitivity of gas-sensitive devices to changes in temperature, humidity, and gas composition, their output response is still easily affected by external noise and environmental disturbances during repeated measurements, resulting in insufficient long-term stability. Furthermore, the bit error rate remains relatively high, and the number of excitation-response pairs is limited, classifying it as a weak PUF structure.

[0006] In summary, while existing sensor-based PUFs possess good uniqueness and randomness, most are weak PUF structures, resulting in a limited number of excitation-response pairs and making it difficult to build a highly reliable, large-scale security authentication system. Furthermore, their output responses are susceptible to noise, temperature drift, and environmental changes, leading to high on-chip Hamming distances, difficulty in reducing bit error rates, and insufficient long-term stability. Moreover, weak PUFs are inherently more sensitive to readout circuitry; when noise suppression is insufficient, response reversals are more likely to occur, further amplifying the bit error rate problem. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a strong PUF circuit for Internet of Things security protection that has high uniqueness and randomness, as well as high stability, low bit error rate and high number of stimulus-response pairs, and can meet the requirements of high reliability and large-scale security authentication system.

[0008] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a strong PUF circuit for IoT security protection, comprising two TMR sensor arrays, two instrumentation amplifiers, two switched-capacitor integrators, and a comparator; each of the two TMR sensor arrays contains N independently selectable TMR sensor units, used to generate differential voltage signals with process randomness based on the input N-bit excitation signal, where N is an integer greater than or equal to 64; the two instrumentation amplifiers are respectively connected to the two TMR sensor arrays, used to perform high common-mode rejection differential amplification on the differential voltage signals output by the two TMR sensor arrays, and output amplified voltage signals; the two switched-capacitor integrators are respectively connected to the two instrumentation amplifiers, used to continuously sample and integrate the amplified voltage signals output by the two instrumentation amplifiers over multiple clock cycles to suppress noise and improve signal stability, and output sampled voltage signals; the comparator is respectively connected to the two switched-capacitor integrators, used to compare the sampled voltage signals output by the two switched-capacitor integrators, and output a decision result as the PUF response.

[0009] Compared with the prior art, the advantage of the present invention is that it constructs a strong PUF circuit by using two TMR sensor arrays (a first TMR sensor array and a second TMR sensor array, respectively), two instrumentation amplifiers (a first instrumentation amplifier and a second instrumentation amplifier, respectively), two switched capacitor integrators (a first switched capacitor integrator and a second switched capacitor integrator, respectively) and a comparator. When a PUF response sequence needs to be generated, the strong PUF circuit works periodically, generating one PUF response in each cycle until the required number of PUF response sequences are obtained.In each cycle, an N-bit excitation signal (i.e., N-bit binary data) is input to the N-bit excitation terminals of the two TMR sensor arrays. In each TMR sensor array, if the excitation signal connected to a certain TMR sensor unit is 1, then that TMR sensor unit is connected to the TMR sensor array; if the excitation signal is 0, then that TMR sensor unit cannot be connected to the TMR sensor array. At this time, each TMR sensor array will output a differential voltage signal. Due to unavoidable slight process variations in the manufacturing of TMR sensor units, there will inevitably be a slight difference between the differential voltage signals output by the first TMR sensor array and the second TMR sensor array. The first instrumentation amplifier outputs a differential voltage signal to the first TMR sensor array. The differential voltage signal output from the sensor array is amplified to obtain an amplified voltage signal, which is then output to a first switched-capacitor integrator. A second instrumentation amplifier amplifies the differential voltage signal output from the second TMR sensor array, obtaining an amplified voltage signal that is also output to a second switched-capacitor integrator. The first switched-capacitor integrator samples, integrates, and accumulates the amplified voltage signal output from the first instrumentation amplifier, obtaining a first sampled voltage signal that is output to a comparator. The second switched-capacitor integrator samples, integrates, and accumulates the amplified voltage signal output from the second instrumentation amplifier, obtaining a second sampled voltage signal that is also output to a comparator. The comparator makes a decision between the first and second sampled voltage signals, obtaining a decision result of "0" or "0". "1" serves as the PUF response output. In this invention, after the two TMR sensor arrays generate unique differential voltage signals, the differential voltage signals output by the two TMR sensor arrays are first differentially amplified with high common-mode rejection by two instrumentation amplifiers to increase the signal amplitude and eliminate common-mode noise and offset, generating an amplified voltage signal output. Subsequently, the amplified voltage signal is sampled and accumulated multiple times over several consecutive clock cycles by two switched-capacitor integrators to achieve time-domain averaging, thereby effectively suppressing transient noise and low-frequency 1 / f noise and improving signal stability. The sampling integration result (i.e., the sampled voltage signal) is then output to the comparator. Finally, the comparator compares the two sampled voltage signals... The signal undergoes voltage polarity determination to obtain a decision result of "0" or "1" as the PUF response. This invention uses two TMR sensor arrays as the core random entropy source module to realize the Physically Unclonable Function (PUF). In each TMR sensor array, the TMR sensor of each TMR sensor unit is a Wheatstone bridge structure composed of four magnetic tunnel junction resistors. When a TMR sensor unit is connected to the TMR sensor array, due to the unavoidable process defects in the manufacturing process of each magnetic tunnel junction resistor, such as differences in magnetic layer thickness, oxide layer uniformity, and junction interface roughness, the resistance values ​​deviate slightly from the ideal values, thereby generating a small and random differential voltage signal at the bridge output.This differential output voltage exhibits statistical independence and non-replicability across different chips, providing a unique physical layer source for the PUF response. Furthermore, to achieve programmable excitation input, each TMR sensor unit in each TMR sensor array is selectively connected to the array via the on / off switching of two switches. This allows the TMR sensor unit to participate in or not participate in PUF response generation, enabling the combination and activation of different TMR sensor units, thereby obtaining 2. N The invention employs a set of excitation-response pairs to achieve strong PUF characteristics, significantly improving the uniqueness and randomness of the PUF response. In addition, the invention adopts a multi-stage signal chain design of "differential detection - precision amplification - integral averaging - comparison decision", which significantly improves the stability and anti-interference capability of the PUF response while ensuring randomness and uniqueness, and has a low bit error rate. Thus, it realizes a highly reliable hardware security authentication scheme that can meet the requirements of a high-reliability, large-scale security authentication system.

[0010] Furthermore, each TMR sensor unit has a positive output terminal, a negative output terminal, and an excitation terminal; the positive output terminals of N TMR sensor units are interconnected to form the positive output terminal of the TMR sensor array, the negative output terminals of N TMR sensor units are interconnected to form the negative output terminal of the TMR sensor array, and the excitation terminals of N TMR sensor units are the N-bit excitation terminals of the TMR sensor array, used to receive N-bit excitation signals; the TMR sensor array outputs differential voltage signals through its positive and negative output terminals.

[0011] Furthermore, each TMR sensor unit includes two electronic switches and one TMR sensor. The TMR sensor has a positive output terminal and a negative output terminal. Each electronic switch has a control terminal, a first terminal, and a second terminal. The two electronic switches are designated as a first switch and a second switch, respectively. The first terminal of the first switch is the positive output terminal of the TMR sensor unit, and the second terminal is connected to the positive output terminal of the TMR sensor. The first terminal of the second switch is connected to the negative output terminal of the TMR sensor, and the second terminal is the negative output terminal of the TMR sensor unit. When a bit of excitation signal is applied to the control terminals of the first and second switches of the TMR sensor unit, if the bit of excitation signal is 1, the TMR sensor unit is connected to the TMR sensor array; if the bit of excitation signal is 0, the TMR sensor unit cannot be connected to the TMR sensor array.

[0012] Furthermore, both instrumentation amplifiers and comparators have positive input terminals, negative input terminals, and output terminals; each switched-capacitor integrator has a first clock terminal, a second clock terminal, an input terminal, and an output terminal. Its first clock terminal is used to connect to a first clock signal CLK1, and its second clock terminal is used to connect to a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are two non-overlapping clocks used to control the switched-capacitor integrator to perform sampling or integration operations. When the first clock signal CLK1 is high and the second clock signal CLK2 is low, the switched-capacitor integrator performs a sampling operation; when the first clock signal CLK1 is low and the second clock signal CLK2 is high, the switched-capacitor integrator performs an integration operation; the two TMR sensor arrays respectively... The system comprises a first TMR sensor array and a second TMR sensor array, two instrumentation amplifiers (IAA and TI), and two switched-capacitor integrators (SCIs). The positive and negative outputs of the first TMR sensor array and the first IIA are connected accordingly. The positive and negative outputs of the second TMR sensor array and the second IIA are also connected accordingly. The output of the first IIA is connected to the input of the first SCI, and the output of the second IIA is connected to the input of the second SCI. The output of the first SCI is connected to the positive input of a comparator, and the output of the second SCI is connected to the negative input of a comparator. The comparator outputs a PUF response through its output.

[0013] Furthermore, the instrumentation amplifier includes a startup circuit, a current reference circuit, a bias circuit, a transconductance equalization circuit, and an operational amplifier circuit. The current reference circuit employs a continuous transconductance structure consisting of four MOSFETs, a first PNP transistor, and a first resistor to provide bias current to the bias circuit, ensuring its normal operation and maintaining a stable bias current during PVT (Process, Voltage, Temperature) changes. The startup circuit includes five MOSFETs to inject current into the current reference circuit upon power-up, preventing it from entering a zero-current state. The bias circuit includes eleven MOSFETs, a second resistor, and a third resistor to convert the bias current into a bias voltage for the transconductance equalization circuit and the operational amplifier circuit to operate normally. The transconductance equalization circuit employs a parallel NMOS transistor structure consisting of 23 MOSFETs. The PMOS differential pair power supply structure is used to make the bias current adaptively change with the common-mode voltage, so as to achieve a constant total transconductance over the entire common-mode voltage range; the operational amplifier circuit includes 28 MOS transistors, a first capacitor and a second capacitor, forming a three-op-amp differential architecture with a rail-to-rail input stage structure and a push-pull linear transconductance ring output stage structure.

[0014] Furthermore, the switched-capacitor integrator includes four electronic switches, a third capacitor, a fourth capacitor, and a first operational amplifier. The first operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The four electronic switches are the third switch, the fourth switch, the fifth switch, and the sixth switch. The first terminal of the third switch is the input terminal of the switched-capacitor integrator. The second terminal of the third switch, the first terminal of the fifth switch, and one terminal of the third capacitor are connected. The other terminal of the third capacitor, the first terminal of the fourth switch, and the first terminal of the sixth switch are connected. The second terminals of the fifth and sixth switches are both grounded. The second terminal of the fourth switch, one terminal of the fourth capacitor, and the non-inverting input terminal of the first operational amplifier are connected. The inverting input terminal of the first operational amplifier is grounded. The other terminal of the fourth capacitor is connected to the output terminal of the first operational amplifier, and its connection terminal is the output terminal of the switched-capacitor integrator. The control terminal of the third switch and the control terminal of the sixth switch are connected, and their connection terminal is the first clock terminal of the switched-capacitor integrator. The control terminal of the fourth switch and the control terminal of the fifth switch are connected, and their connection terminal is the second clock terminal of the switched-capacitor integrator.

[0015] Furthermore, the strong PUF circuit for IoT security protection also includes an excitation distributor. The excitation distributor generates N-bit binary data, i.e., N-bit excitation signals, based on externally input excitation, and outputs them to the N-bit excitation terminals of the first TMR sensor array and the second TMR sensor array respectively, thereby controlling the number of TMR sensor units connected in the first TMR sensor array and the second TMR sensor array. Attached Figure Description

[0016] Figure 1 This is a block diagram of the robust PUF circuit structure for IoT security protection according to the present invention;

[0017] Figure 2 This is a schematic diagram of the TMR sensor array of the strong PUF circuit for IoT security protection according to the present invention.

[0018] Figure 3 This is a circuit diagram of the TMR sensor unit of the strong PUF circuit for IoT security protection according to the present invention.

[0019] Figure 4 This is a circuit diagram of an instrumentation amplifier for a strong PUF circuit used for IoT security protection according to the present invention.

[0020] Figure 5 This is a circuit diagram of the integrator of the strong PUF circuit for Internet of Things security protection according to the present invention;

[0021] Figure 6The on-chip and off-chip Hamming distance distribution diagram for the strong PUF circuit for IoT security protection of the present invention when the two switched capacitor integrators are omitted;

[0022] Figure 7 This is a diagram showing the on-chip and off-chip Hamming distance distribution of the strong PUF circuit for IoT security protection according to the present invention;

[0023] Figure 8 The diagram shows a comparison of the bit error rate distribution of the strong PUF circuit for IoT security protection of the present invention with that formed by omitting two switched capacitor integrators under different voltage conditions.

[0024] Figure 9 This is a comparison chart showing the bit error rate distribution of the strong PUF circuit for IoT security protection of the present invention with that formed by omitting two switched capacitor integrators under different temperature conditions. Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Example 1: As Figure 1 As shown, a robust PUF circuit for IoT security protection includes two TMR sensor arrays, two instrumentation amplifiers, two switched-capacitor integrators, and a comparator; the TMR sensor arrays include N TMR sensor units, where N is an integer greater than or equal to 64; as shown... Figure 2 As shown, each TMR sensor unit has a positive output terminal, a negative output terminal, and an excitation terminal; the positive output terminals of N TMR sensor units are connected together, and their connection terminals form the positive output terminals of the TMR sensor array; the negative output terminals of N TMR sensor units are connected together, and their connection terminals form the negative output terminals of the TMR sensor array; the excitation terminals of the N TMR sensor units form the N-bit excitation terminals of the TMR sensor array; as shown... Figure 3As shown, each TMR sensor unit includes two electronic switches and one TMR sensor. The TMR sensor has a positive output terminal and a negative output terminal. Each electronic switch has a control terminal, a first terminal, and a second terminal. When its control terminal is connected to a high level, its first terminal and second terminal are connected; when its control terminal is connected to a low level, its first terminal and second terminal are disconnected. The two electronic switches are a first switch S1 and a second switch S2. The first terminal of the first switch S1 is the positive output terminal of the TMR sensor unit, and its second terminal is connected to the positive output terminal of the TMR sensor. The first terminal of the second switch S2 is connected to the negative output terminal of the TMR sensor. The output terminal is connected, and the second terminal is the negative output terminal of the TMR sensor unit; both the instrumentation amplifier and comparator have positive input terminals, negative input terminals, and output terminals; the switched capacitor integrator has a first clock terminal, a second clock terminal, an input terminal, and an output terminal. Its first clock terminal is used to input the first clock signal CLK1, and the second clock terminal is used to input the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are two non-overlapping clocks used to control the switched capacitor integrator to perform sampling or integration operations. When the first clock signal CLK1 is high and the second clock signal CLK2 is low... When the clock signal CLK1 is low and the clock signal CLK2 is high, the switched-capacitor integrator performs sampling. When the first clock signal CLK1 is low and the second clock signal CLK2 is high, the switched-capacitor integrator performs integration. The two TMR sensor arrays are referred to as the first TMR sensor array and the second TMR sensor array, respectively. The two instrumentation amplifiers are referred to as the first instrumentation amplifier and the second instrumentation amplifier, respectively. The two switched-capacitor integrators are referred to as the first switched-capacitor integrator and the second switched-capacitor integrator, respectively. The positive output terminal of the first TMR sensor array is connected to the positive input terminal of the first instrumentation amplifier, and the negative output terminal of the first TMR sensor array is connected to the negative input terminal of the first instrumentation amplifier. The positive output terminal of the second TMR sensor array is connected to the positive input terminal of the second instrumentation amplifier, and the negative output terminal of the second TMR sensor array is connected to the negative input terminal of the second instrumentation amplifier. The output terminal of the first instrumentation amplifier is connected to the input terminal of the first switched-capacitor integrator, and the output terminal of the second instrumentation amplifier is connected to the input terminal of the second switched-capacitor integrator. The output terminal of the first switched-capacitor integrator is connected to the positive input terminal of the comparator, and the output terminal of the second switched-capacitor integrator is connected to the negative input terminal of the comparator. The output terminal of the comparator is used to output the response.

[0027] In this embodiment, when a PUF response sequence needs to be generated, the strong PUF circuit works periodically, generating one PUF response in each cycle until the required number of PUF response sequences are obtained.In each cycle, N-bit excitation signals (i.e., N-bit binary data) are connected to the N-bit excitation terminals of the two TMR sensor arrays. In each TMR sensor array, the control terminals of the first switch S1 and the second switch S2 of each TMR sensor unit are respectively connected to one bit of excitation signal. If the excitation signal bit is 1, the TMR sensor unit is connected to the TMR sensor array; if the excitation signal bit is 0, the TMR sensor unit cannot be connected to the TMR sensor array. At this time, the positive and negative output terminals of each TMR sensor array will output differential voltage signals. Due to unavoidable process variations in the manufacturing of TMR sensor units, the positive and negative output terminals of the first and second TMR sensor arrays... The differential voltage signals output from the positive and negative output terminals will inevitably have a slight difference. The first instrumentation amplifier amplifies the differential voltage signal output from the first TMR sensor array, and the amplified voltage signal is output to the first switched-capacitor integrator. The second instrumentation amplifier amplifies the differential voltage signal output from the second TMR sensor array, and the amplified voltage signal is output to the second switched-capacitor integrator. The first switched-capacitor integrator samples, integrates, and accumulates the amplified voltage signal output from the first instrumentation amplifier, and outputs the first sampled voltage signal to the comparator. The second switched-capacitor integrator samples, integrates, and accumulates the amplified voltage signal output from the second instrumentation amplifier, and outputs the second sampled voltage signal to the comparator. The comparator then compares the first sampled voltage signal... The first and second sampled voltage signals are used to make a decision, and the decision result "0" or "1" is used as the PUF response output. In this invention, after the two TMR sensor arrays generate unique differential voltage signals, the differential voltage signals output by the two TMR sensor arrays are first differentially amplified with high common-mode rejection by two instrumentation amplifiers to increase the signal amplitude and eliminate common-mode noise and offset, generating an amplified voltage signal output. Then, the amplified voltage signal is sampled and accumulated multiple times in several consecutive clock cycles by two switched-capacitor integrators to achieve time-domain averaging, thereby effectively suppressing transient noise and low-frequency 1 / f noise and improving signal stability. The sampling integration result (i.e., the sampled voltage signal) is then output to the comparator. Finally, the comparator performs voltage polarity determination on the two integral results to obtain a decision result of "0" or "1" as the PUF response. This invention uses two TMR sensor arrays as the core random entropy source module to realize the Physically Unclonable Function (PUF). In each TMR sensor array, the TMR sensor of each TMR sensor unit is a Wheatstone bridge structure composed of four magnetic tunnel junction resistors. When a TMR sensor unit is connected to the TMR sensor array, due to the unavoidable process defects in the manufacturing process of each magnetic tunnel junction resistor, such as differences in magnetic layer thickness, oxide layer uniformity, and junction interface roughness, the resistance values ​​deviate slightly from the ideal values, thereby generating a small and random differential voltage signal at the bridge output.This differential output voltage exhibits statistical independence and non-replicability across different chips, providing a unique physical layer source for the PUF response. Furthermore, to achieve programmable excitation input, each TMR sensor unit in each TMR sensor array is selectively connected to the array via the on / off switching of two switches. This allows the TMR sensor unit to participate in or not participate in PUF response generation, enabling the combination and activation of different TMR sensor units, thereby obtaining 2. N The invention employs a set of excitation-response pairs to achieve strong PUF characteristics, significantly improving the uniqueness and randomness of the PUF response. In addition, the invention adopts a multi-stage signal chain design of "differential detection - precision amplification - integral averaging - comparison decision", which significantly improves the stability and anti-interference capability of the PUF response while ensuring randomness and uniqueness, and has a low bit error rate. Thus, it realizes a highly reliable hardware security authentication scheme that can meet the requirements of a high-reliability, large-scale security authentication system.

[0028] Example 2: This example is basically the same as Example 1, except that: In this example, the strong PUF circuit for IoT security protection also includes an excitation distributor. The excitation distributor generates N-bit binary data, i.e., N-bit excitation signals, according to the externally input excitation, and outputs them to the N-bit excitation terminals of the first TMR sensor array and the second TMR sensor array respectively, thereby controlling the number of TMR sensor units connected in the first TMR sensor array and the second TMR sensor array.

[0029] Example 3: This example is basically the same as Example 1, except that: in this example, as Figure 4 As shown, the instrumentation amplifier includes a startup circuit, a current reference circuit, a bias circuit, a transconductance equalization circuit, and an operational amplifier circuit. The current reference circuit uses a continuous transconductance structure consisting of four MOSFETs, a first PNP transistor P1, and a first resistor R1 to provide bias current for the bias circuit, enabling it to operate normally and maintaining a stable bias current when the PVT changes. The startup circuit includes five MOSFETs to inject current when the current reference circuit is powered on, preventing the current reference circuit from entering a zero-current state when powered on. The bias circuit includes 11 MOSFETs, a second resistor R2, and a third resistor R3 to convert the bias current into a bias voltage for the transconductance equalization circuit and the operational amplifier circuit to operate normally. The transconductance equalization circuit uses a parallel NMOS / PMOS differential pair power supply structure consisting of 23 MOSFETs to make the bias current adaptively change with the common-mode voltage, achieving a constant total transconductance across the entire common-mode voltage range. The operational amplifier circuit includes 28 MOSFETs, a first capacitor C1, and a second capacitor C2, forming a three-op-amp differential architecture with a rail-to-rail input stage and a push-pull linear transconductance ring output stage.

[0030] In this embodiment, the four MOSFETs in the current reference circuit are designated as the fifth MOSFET M5, the sixth MOSFET M6, the eighth MOSFET M8, and the ninth MOSFET M9; the five MOSFETs in the startup circuit are designated as the first MOSFET M1 to the fourth MOSFET M4 and the seventh MOSFET M7; the eleven MOSFETs in the bias circuit are designated as the tenth MOSFET M10 to the twentieth MOSFET M20; the twenty-three MOSFETs in the transconductance equalization circuit are designated as the twenty-first MOSFET M21 to the forty-third MOSFET M43; the twenty-eight MOSFETs in the operational amplifier circuit are designated as the forty-fourth MOSFET M44 to the seventy-first MOSFET M71; the fourth MOSFET M4, the seventh MOSFET M7, the ninth MOSFET M9, the eleventh MOSFET M11, the twelfth MOSFET M12, the thirteenth MOSFET M13, the fourteenth MOSFET M14, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-second MOSFET M22, and the twenty-fifth MOSFET M9. S-MOSFET M25, 27th MOSFET M27, 29th MOSFET M29, 31st MOSFET M31, 32nd MOSFET M32, 34th MOSFET M34, 35th MOSFET M35, 36th MOSFET M36, 37th MOSFET M37, 39th MOSFET M39, 40th MOSFET M40, 43rd MOSFET M43, 45th MOSFET M45, 46th MOSFET M46, 47th MOSFET M47, 48th MOSFET M48, 53rd MOSFET M53, 54th MOSFET M54, 55th MOSFET M55, 56th MOSFET M56, 60th MOSFET M60, 61st MOSFET M61, 64th MOSFET M64, 65th MOSFET M65, 68th MOSFET M68, 69th MOSFET M69, and 71st MOSFET M71 are all NMOS transistors;MOSFETs M1 (first), M2 (second), M3 (third), M5 (fifth), M6 (sixth), M8 (eighth), M10 (tenth), M15 (fifth), M16 (sixteenth), M17 (seventeenth), M18 (eighth), M21 (twenty-first), M23 (twenty-third), M24 (twenty-fourth), M26 (twenty-sixth), M28 (twenty-eighth), M30 (thirtieth), M33 (thirty-third), M38 (thirty-eighth), M31 (fortieth) MOSFETs M41, M42, M44, M49, M50, M51, M52, M57, M58, M59, M62, M63, M66, M67, and M70 are all PMOS transistors; the source of MOSFET M1, the source of MOSFET M5, and the source of MOSFET M70 are all PMOS transistors. The sources of transistors M8, M10 (10th), M15 (15th), M17 (17th), M21 (21st), M24 (24th), M28 (28th), M50 (50th), M57 (57th), M62 (62nd), M66 (66th), and M70 (70th) are all connected to the power supply voltage VDD; the drains of transistors M31 (31st), M35 (35th), and M70 (40th) are connected to the power supply voltage VDD. The drains of MOSFET M40 and the forty-fifth MOSFET M45 are both connected to the power supply voltage VDD; the gate and drain of the first MOSFET M1 and the source of the second MOSFET M2 are connected; the gate and drain of the second MOSFET M2 and the source of the third MOSFET M3 are connected; the gate of the third MOSFET M3, the gate of the fourth MOSFET M4, the drain of the fifth MOSFET M5, the drain and gate of the sixth MOSFET M6, the source of the seventh MOSFET M7 and the gate of the ninth MOSFET M9 are connected; the drain of the third MOSFET M3, the drain of the fourth MOSFET M4 and the gate of the seventh MOSFET M7 are connected.The source of the fourth MOSFET M4, the collector and base of the first PNP transistor P1, one end of the first resistor R1, the source of the twelfth MOSFET M12, the source of the fourteenth MOSFET M14, the source of the twentieth MOSFET M20, the source of the twenty-second MOSFET M22, the source of the twenty-fifth MOSFET M25, the source of the twenty-seventh MOSFET M27, the source of the twenty-ninth MOSFET M29, the drain of the thirtieth MOSFET M30, the source of the thirty-second MOSFET M32, the source of the thirty-fourth MOSFET M34, the source of the thirty-seventh MOSFET M37, the source of the thirty-ninth MOSFET M39, the source of the forty-third MOSFET M43, the source of the forty-seventh MOSFET M47, the fifth... The sources of MOSFETs M54 (fourteenth), M61 (sixty-first), M65 (sixty-fifth), M69 (sixty-ninth), and M71 (seventy-first) are all grounded; the gates of MOSFETs M5 and M8, M7 and M9, and M10 are connected; the source of MOSFET M6 is connected to the emitter of P1; the source of MOSFET M9 is connected to the other end of resistor R1; the drains of MOSFET M10, M11, and M13 are connected; the eleventh MOSFET... The source of transistor M11, the drain and gate of the twelfth MOSFET M12, and the gate of the fourteenth MOSFET M14 are connected; the source of the thirteenth MOSFET M13 and the drain of the fourteenth MOSFET M14 are connected; the drain of the thirteenth MOSFET M13, the gate of the sixteenth MOSFET M16, the gate of the eighteenth MOSFET M18, one end of the second resistor R2, the gate of the fifty-first MOSFET M51, the gate of the fifty-eighth MOSFET M58, and the gate of the sixty-seventh MOSFET M67 are connected; the drain of the fifteenth MOSFET M15 and the source of the sixteenth MOSFET M16 are connected; the gate of the fifteenth MOSFET M15, the drain of the sixteenth MOSFET M16, the gate of the seventeenth MOSFET M17, and the second resistor R2 are connected. The other end is connected; the drain of the seventeenth MOSFET M17 and the source of the eighteenth MOSFET M18 are connected; the drain of the eighteenth MOSFET M18, one end of the third resistor R3, the gate of the nineteenth MOSFET M19, the gate of the fifty-third MOSFET M53, the gate of the sixtieth MOSFET, and the gate of the sixty-fourth MOSFET M64 are connected; the drain of the nineteenth MOSFET M19, the other end of the third resistor R3, the gate of the twentieth MOSFET M20, the gate of the thirty-second MOSFET M32, the gate of the thirty-ninth MOSFET M39, the gate of the forty-seventh MOSFET M47, and the gate of the sixty-fifth MOSFET M65 are connected; the source of the nineteenth MOSFET M19 and the drain of the twentieth MOSFET M20 are connected;The drain of the 21st MOSFET M21 is connected to the drain of the 22nd MOSFET M22; the gate of the 21st MOSFET M21 is connected to the gate of the 28th MOSFET M28; the gate of the 22nd MOSFET M22, the gate and drain of the 23rd MOSFET M23, and the drain of the 25th MOSFET M25 are connected; the source of the 23rd MOSFET M23, the drain of the 24th MOSFET M24, and the source of the 26th MOSFET M26 are connected; the gate of the 24th MOSFET M24, the gate of the 31st MOSFET M31, the gate of the 35th MOSFET M35, the gate of the 40th MOSFET M40, the gate of the 45th MOSFET M45, and the 60th MOSFET M26 are connected to the drain of the 21st MOSFET M21, the gate of the 22nd MOSFET M22, the gate of the 23rd MOSFET M23, and the drain of the 25th MOSFET M25 are connected; The gate connection of MOSFET M66 is as follows: The gate of MOSFET M25 (25th), the drain of MOSFET M26 (26th), and the gate and drain of MOSFET M27 (27th) are connected; The gate of MOSFET M26 (26th), the drain of MOSFET M28 (28th), the gate and drain of MOSFET M29 (29th), and the gate connection of MOSFET M30 are as follows: The source of MOSFET M30 (30th), the source of MOSFET M31 (31st), the drain of MOSFET M32 (32nd), and the source of MOSFET M33 (33rd) are connected; The gate and drain of MOSFET M33 (33rd), the drain of MOSFET M34 (34th), and the gate connection of MOSFET M36 (36th) are as follows: The gate of the 34th MOSFET M34, the gate and drain of the 37th MOSFET M37, and the drain of the 36th MOSFET M36 are connected; the source of the 35th MOSFET M35, the source of the 36th MOSFET M36, and the source of the 38th MOSFET M38 are connected; the drain of the 38th MOSFET M38 and the drain of the 39th MOSFET M39 are connected; the gate of the 38th MOSFET M38 and the gate of the 43rd MOSFET M43 are connected; the source of the 40th MOSFET M40, the source of the 41st MOSFET M41, and the source of the 42nd MOSFET M42 are connected; the gate of the 41st MOSFET M41, the gate of the 48th MOSFET M48, and the drain of the 35th MOSFET M35, the source of the 36th MOSFET M36, and the source of the 38th MOSFET M38 are connected; The gate of MOSFET M49 (49th MOSFET) is connected to the positive input terminal of the instrumentation amplifier; the drains of MOSFETs M41 (41st MOSFET), M42 (42nd MOSFET), and M43 (43rd MOSFET) are connected; the gates of MOSFETs M42 (42nd MOSFET), M44 (44th MOSFET), and M46 (46th MOSFET) are connected, and their connection terminals are the negative input terminals of the instrumentation amplifier; the sources of MOSFETs M44 (44th MOSFET), M45 (45th MOSFET), and M49 (49th MOSFET) are connected; the drains of MOSFETs M44 (44th MOSFET), M54 (54th MOSFET), and M53 (53rd MOSFET) are connected.The drain of the 46th MOSFET M46, the drain of the 57th MOSFET M57, the source of the 58th MOSFET M58, and one end of the first capacitor C1 are connected; the source of the 46th MOSFET M46, the source of the 48th MOSFET M48, and the drain of the 47th MOSFET M47 are connected; the drain of the 48th MOSFET M48, the drain of the 50th MOSFET M50, and the source of the 51st MOSFET M51 are connected; the drain of the 49th MOSFET M49, the source of the 60th MOSFET M60, the drain of the 61st MOSFET M61, and one end of the second capacitor C2 are connected. Connections: The gate of MOSFET M50, the drain of MOSFET M51, the source of MOSFET M52, the drain of MOSFET M55, and the gate of MOSFET M57 are connected; The gate of MOSFET M52, the gate of MOSFET M59, the gate and drain of MOSFET M63, and the drain of MOSFET M64 are connected; The drain of MOSFET M52, the drain of MOSFET M53, the source of MOSFET M55, and the gate of MOSFET M54 are connected. The gate connection of MOSFET M61 (61st MOSFET); the gate connection of MOSFET M55 (55th MOSFET), MOSFET M56 (56th MOSFET), MOSFET M67 (67th MOSFET), and MOSFET M68 (68th MOSFET); the connection of the drain of MOSFET M56 (56th MOSFET), MOSFET M58 (58th MOSFET), MOSFET M59 (59th MOSFET), and MOSFET M70 (70th MOSFET); the connection of the source of MOSFET M56 (56th MOSFET), MOSFET M59 (59th MOSFET), MOSFET M60 (60th MOSFET), and MOSFET M71 (71st MOSFET). The gate and drain of MOSFET M62 (62nd MOSFET) and the source of MOSFET M63 (63rd MOSFET) are connected; the source of MOSFET M64 (64th MOSFET) and the drain of MOSFET M65 (65th MOSFET) are connected; the drain of MOSFET M66 (66th MOSFET) and the source of MOSFET M67 (67th MOSFET) are connected; the source of MOSFET M68 (68th MOSFET) and the drain and gate of MOSFET M69 (69th MOSFET) are connected; the drain of MOSFET M70 (70th MOSFET) and MOSFET M71 (71st MOSFET), the other end of capacitor C1, and the other end of capacitor C2 are connected, and their connection points are the output terminals of the instrumentation amplifier.

[0031] In this embodiment, each instrumentation amplifier is positioned between a TMR sensor array and a switched capacitor integrator. Its operational amplifier circuit adopts a three-op-amp differential architecture and introduces a rail-to-rail input stage and a push-pull linear transconductance loop output stage structure to ensure stable gain and high linearity under low power supply voltage and wide dynamic range conditions. This allows for precise amplification of the millivolt-level differential voltage generated by the TMR sensor array under the excitation voltage, ensuring the accuracy and reliability of the subsequent response. When the instrumentation amplifier is powered on, the first MOSFET M1 and the second MOSFET M2 in the startup circuit convert voltage into current, which is then injected into the current reference circuit through the seventh MOSFET M7. The current reference circuit generates a pre-set current value. Due to its continuous transconductance structure, the current reference circuit can maintain a constant output under PVT changes. The stable output bias current is converted into a bias voltage through the bias circuit and provided to the transconductance equalization circuit and the operational amplifier circuit, enabling the transconductance equalization circuit and the operational amplifier circuit to work normally. When the voltages of the forty-fourth MOSFET M44, forty-sixth MOSFET M46, forty-eighth MOSFET M48, and forty-ninth MOSFET M49 in the operational amplifier circuit change, the transconductance equalization circuit will adaptively adjust according to the bias current to keep the transconductance of the forty-fourth MOSFET M44, forty-sixth MOSFET M46, forty-eighth MOSFET M48, and forty-ninth MOSFET M49 constant.

[0032] Example 4: This example is basically the same as Example 3, except that: in this example, as Figure 5 As shown, the switched-capacitor integrator includes four electronic switches, a third capacitor C3, a fourth capacitor C4, and a first operational amplifier A1. The first operational amplifier A1 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The four electronic switches are the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6. The first terminal of the third switch S3 is the input terminal of the switched-capacitor integrator. The second terminal of the third switch S3, the first terminal of the fifth switch S5, and one terminal of the third capacitor C3 are connected. The other terminal of the third capacitor C3, the first terminal of the fourth switch S4, and the first terminal of the sixth switch S6 are connected. The fifth switch... The second terminals of switches S5 and S6 are both grounded. The second terminal of switch S4, one terminal of capacitor C4, and the non-inverting input of op-amp A1 are connected. The inverting input of op-amp A1 is grounded. The other terminal of capacitor C4 is connected to the output of op-amp A1, and its connection terminal is the output of the switched capacitor integrator. The control terminal of switch S3 is connected to the control terminal of switch S6, and its connection terminal is the first clock terminal of the switched capacitor integrator. The control terminal of switch S4 is connected to the control terminal of switch S5, and its connection terminal is the second clock terminal of the switched capacitor integrator.

[0033] In this switched-capacitor integrator, when the first clock signal CLK1 is connected to the first clock terminal and the second clock signal CLK2 is connected to the second clock terminal, if the first clock signal CLK1 is high and the second clock signal CLK2 is low, then the third switch S3 and the sixth switch S6 are closed, the fourth switch S4 and the fifth switch S5 are open, and the fourth capacitor C4 and the first operational amplifier A1 are disconnected from the input terminal of the switched-capacitor integrator. The third switch S3, the third capacitor C3, and the sixth switch S6 form a sampling path to charge the third capacitor C3 and perform sampling operations. When the first clock signal CLK1 is low and the second clock signal CLK2 is high, then the third switch S3 and the sixth switch S6 are open, the fourth switch S4 and the fifth switch S5 are closed, and the third capacitor C3 is disconnected from the input terminal of the switched-capacitor integrator. One end of the third capacitor C3 is grounded through the fifth switch S5. The third capacitor C3, the fourth switch S4, the fourth capacitor C4, and the first operational amplifier A1 form an integration path to transfer the charge on the third capacitor C3 to the fourth capacitor C4, thereby realizing the integration operation.

[0034] To verify the performance of the strong PUF circuit for IoT security of the present invention, a complete circuit model of the strong PUF circuit for IoT security of the present invention and a complete circuit model of a comparison PUF were built on the Cadence Virtuoso platform. In the comparison PUF, the performance of the strong PUF circuit for IoT security of the present invention was improved by removing two switched-capacitor integrators and directly connecting two instrumentation amplifiers to the comparator, forming a PUF structure. Monte Carlo simulation was used to systematically evaluate the randomness, uniqueness, and stability of the strong PUF circuit for IoT security of the present invention and the comparison PUF.

[0035] The performance indicators of randomness and uniqueness of PUF mainly include off-chip Hamming distance (Inter-HD, ideal value 50%) and on-chip Hamming distance (Intra-HD, ideal value 0%). Sixty-four strong PUF circuits for IoT security protection of this invention and a comparison PUF were repeatedly excited, and the on-chip and off-chip Hamming distance distribution of the comparison PUF was obtained as follows: Figure 6 As shown, the on-chip and off-chip Hamming distance distribution diagram of the strong PUF circuit for IoT security protection of the present invention is as follows: Figure 7 As shown. Analysis Figure 6 It can be seen that, compared to PUF, the inter-HD distance is 0.4925 (standard deviation 0.1150), while the intra-HD mean is approximately 0.0344 (standard deviation 0.0176). Analysis Figure 7It can be seen that the off-chip Hamming distance Inter-HD of the strong PUF circuit for IoT security protection in this invention is improved to 0.5046, which is closer to the theoretical ideal value of 50%, reflecting a further enhancement of randomness. At the same time, Intra-HD is significantly reduced, with its mean decreasing to 0.0045 and its standard deviation being only 0.0025, indicating a significant improvement in repeatability consistency. (Comparison) Figure 6 and Figure 7 As can be seen, the strong PUF circuit for IoT security protection of the present invention, after introducing a switched capacitor integrator, accumulates the amplified voltage signal output by the instrumentation amplifier in the time domain through the switched capacitor integrator, suppressing high-frequency noise and transient disturbances, and significantly improving the randomness and uniqueness of PUF.

[0036] To further verify the impact of the switched-capacitor integrator of the strong PUF circuit for IoT security protection of the present invention on the bit error rate under environmental changes, the effects of voltage and temperature on the stability of the strong PUF circuit for IoT security protection of the present invention were tested respectively.

[0037] The robust PUF circuit for IoT security protection of this invention, along with a comparative PUF, were tested for bit error rate under 18 conditions, with a temperature of 25°C and a power supply voltage of VDD of 1.8V as reference points. Figure 8 The figure shows a comparison of the bit error rate distribution under different voltage conditions. The 18 scenarios are as follows: Temperature 25℃, power supply voltage VDD 1.7V; Temperature 25℃, power supply voltage VDD 1.8V; Temperature 25℃, power supply voltage VDD 1.9V; Temperature 30℃, power supply voltage VDD 1.7V; Temperature 30℃, power supply voltage VDD 1.8V; Temperature 30℃, power supply voltage VDD 1.9V; Temperature 35℃, power supply voltage VDD 1.7V; Temperature 35℃, power supply voltage VDD 1.8V; Temperature 35℃, power supply voltage VDD 1.9V; Temperature 40℃, power supply voltage VDD 1.7V; Temperature 40℃, power supply voltage VDD 1.8V; Temperature 40℃, power supply voltage VDD 1.9V; Temperature 45℃, power supply voltage VDD 1.7V; Temperature 45℃, power supply voltage VDD 1.8V; Temperature 45℃, power supply voltage VDD 1.9V; Temperature 50℃, power supply voltage VDD... 1.7V; at 50℃, power supply voltage VDD 1.8V; at 50℃, power supply voltage VDD 1.9V. Figure 8 In this context, PUF represents the bit error rate distribution curve of the PUF under different voltage conditions, while PUF (after integration) represents the bit error rate distribution curve of the strong PUF circuit for IoT security protection of this invention as a function of voltage. Analysis Figure 8It can be seen that the strong PUF circuit for IoT security protection of the present invention has a low bit error rate, which is 1.17% in the worst case, compared with the higher bit error rate of the conventional PUF, which is 2.73% in the worst case. Therefore, it can be seen that the strong PUF circuit for IoT security protection of the present invention has high stability under different voltages.

[0038] The strong PUF circuit for IoT security protection of the present invention and a comparative PUF were subjected to bit error rate tests of PUF response at different temperatures. The temperature test range was 25-50℃, with 25℃ as the reference point. PUF(1), PUF(2), and PUF(3) represent the temperature change curves of three different PUF responses generated by the comparative example, and PUF_Int(1), PUF_Int(2), and PUF_Int(3) represent the temperature change curves of three different PUF responses generated by the strong PUF circuit for IoT security protection of the present invention. PUF(1) and PUF_Int(1) correspond to the output of the same PUF response under different circuit structures, PUF(2) and PUF_Int(2) correspond to the output of the same PUF response under different circuit structures, and PUF(3) and PUF_Int(3) correspond to the output of the same PUF response under different circuit structures. Analysis Figure 9 It can be seen that the strong PUF circuit for IoT security protection of the present invention has a significantly lower bit error rate in its PUF response when the temperature changes compared to the comparative PUF. This verifies that the strong PUF circuit for IoT security protection of the present invention has high stability at different temperatures.

[0039] In summary, the strong PUF circuit for IoT security protection of the present invention has high uniqueness and randomness, as well as high stability, low bit error rate and high number of stimulus-response pairs, which can meet the requirements of high reliability and large-scale security authentication system.

Claims

1. A robust PUF circuit for IoT security protection, characterized in that, The system includes two TMR sensor arrays, two instrumentation amplifiers, two switched-capacitor integrators, and a comparator. Each TMR sensor array contains N independently selectable TMR sensor units, used to generate a differential voltage signal with process randomness based on an N-bit input excitation signal, where N is an integer greater than or equal to 64. The two instrumentation amplifiers are connected to the two TMR sensor arrays respectively, used to differentially amplify the differential voltage signals output by the two TMR sensor arrays and output amplified voltage signals. The two switched-capacitor integrators are connected to the two instrumentation amplifiers respectively, used to continuously sample and integrate the amplified voltage signals output by the two instrumentation amplifiers over multiple clock cycles, and output sampled voltage signals. The comparator is connected to the two switched-capacitor integrators respectively, used to compare the sampled voltage signals output by the two switched-capacitor integrators, and outputs a decision result as a PUF response.

2. The robust PUF circuit for IoT security protection according to claim 1, characterized in that, Each TMR sensor unit has a positive output terminal, a negative output terminal, and an excitation terminal; the positive output terminals of N TMR sensor units are interconnected to form the positive output terminal of the TMR sensor array, the negative output terminals of N TMR sensor units are interconnected to form the negative output terminal of the TMR sensor array, and the excitation terminals of N TMR sensor units are the N-bit excitation terminals of the TMR sensor array, used to receive N-bit excitation signals; the TMR sensor array outputs differential voltage signals through its positive and negative output terminals.

3. The robust PUF circuit for IoT security protection according to claim 2, characterized in that, Each TMR sensor unit includes two electronic switches and one TMR sensor. The TMR sensor has a positive output terminal and a negative output terminal. Each electronic switch has a control terminal, a first terminal, and a second terminal. The two electronic switches are a first switch and a second switch, respectively. The first terminal of the first switch is the positive output terminal of the TMR sensor unit, and the second terminal is connected to the positive output terminal of the TMR sensor. The first terminal of the second switch is connected to the negative output terminal of the TMR sensor, and the second terminal is the negative output terminal of the TMR sensor unit.

4. The robust PUF circuit for IoT security protection according to claim 2, characterized in that, Both instrumentation amplifiers and comparators have positive input, negative input, and output terminals; each switched-capacitor integrator has a first clock terminal, a second clock terminal, an input terminal, and an output terminal; the two TMR sensor arrays are a first TMR sensor array and a second TMR sensor array, respectively; the two instrumentation amplifiers are a first instrumentation amplifier and a second instrumentation amplifier, respectively; and the two switched-capacitor integrators are a first switched-capacitor integrator and a second switched-capacitor integrator, respectively. The positive and negative output terminals of the first TMR sensor array and the first instrumentation amplifier are connected accordingly. The positive and negative output terminals of the second TMR sensor array and the second instrumentation amplifier are connected accordingly. The output terminal of the first instrumentation amplifier is connected to the input terminal of the first switched-capacitor integrator. The output terminal of the second instrumentation amplifier is connected to the input terminal of the second switched-capacitor integrator. The output terminal of the first switched-capacitor integrator is connected to the positive input terminal of the comparator. The output terminal of the second switched-capacitor integrator is connected to the negative input terminal of the comparator. The comparator outputs a PUF response through its output terminal.

5. The robust PUF circuit for IoT security protection according to claim 4, characterized in that, The instrumentation amplifier includes a startup circuit, a current reference circuit, a bias circuit, a transconductance equalization circuit, and an operational amplifier circuit; the current reference circuit adopts a continuous transconductance structure to provide a stable bias current for the bias circuit so that it can work normally. The startup circuit is used to inject current when the current reference circuit is powered on, to prevent the current reference circuit from entering a zero current state when powered on. The bias circuit is used to convert the bias current into a bias voltage so that the transconductance equalization circuit and the operational amplifier circuit can work normally. The transconductance equalization circuit adopts a parallel NMOS PMOS differential pair power supply structure to enable the bias current to adapt to the common-mode voltage and achieve total transconductance stability. The operational amplifier circuit adopts a three-op-amp differential architecture with a rail-to-rail input stage structure and a push-pull linear transconductance loop output stage structure.

6. The robust PUF circuit for IoT security protection according to claim 5, characterized in that, The continuous transconductance structure is composed of 4 MOSFETs, a first PNP transistor, and a first resistor; the startup circuit includes 5 MOSFETs; the bias circuit includes 11 MOSFETs, a second resistor, and a third resistor; the transconductance equalization circuit includes 23 MOSFETs; and the operational amplifier circuit includes 28 MOSFETs, a first capacitor, and a second capacitor.

7. The robust PUF circuit for IoT security protection according to claim 4, characterized in that, The switched-capacitor integrator includes four electronic switches, a third capacitor, a fourth capacitor, and a first operational amplifier. The first operational amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The four electronic switches are the third switch, the fourth switch, the fifth switch, and the sixth switch. The first terminal of the third switch is the input terminal of the switched-capacitor integrator. The second terminal of the third switch, the first terminal of the fifth switch, and one terminal of the third capacitor are connected. The other terminal of the third capacitor, the first terminal of the fourth switch, and the first terminal of the sixth switch are connected. The second terminals of the fifth and sixth switches are both grounded. The second terminal of the fourth switch, one terminal of the fourth capacitor, and the non-inverting input terminal of the first operational amplifier are connected. The inverting input terminal of the first operational amplifier is grounded. The other terminal of the fourth capacitor is connected to the output terminal of the first operational amplifier, and its connection terminal is the output terminal of the switched-capacitor integrator. The control terminal of the third switch and the control terminal of the sixth switch are connected, and their connection terminal is the first clock terminal of the switched-capacitor integrator. The control terminal of the fourth switch and the control terminal of the fifth switch are connected, and their connection terminal is the second clock terminal of the switched-capacitor integrator.

8. The robust PUF circuit for IoT security protection according to claim 2, characterized in that, It also includes an excitation distributor, which generates N-bit binary data, i.e. N-bit excitation signals, based on externally input excitation, and outputs them to the N-bit excitation terminals of the two TMR sensor arrays respectively, thereby controlling the number of TMR sensor units connected in the two TMR sensor arrays.

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