Stage circuit, display device including the same, and electronic device including the same

Abstract

Embodiments of the present disclosure may provide a stage circuit comprising: a first input terminal into which a clock signal is input; a second input terminal into which a driving signal is input; an output terminal for outputting a carry signal; an input unit configured to transmit a driving signal to a first node in response to a clock signal; a signal processing unit for controlling the voltages of a Q node and a QB node in response to a driving signal input to the first node; and a carry output unit comprising a boosting capacitor connected to the Q node and the output terminal, respectively, and a buffer capacitor configured to maintain the voltage of the output terminal. According to the stage circuit according to the embodiments of the present disclosure, a display device including the same, and an electronic device including the same, the polling time of the carry signal can be shortened.

Description

Technology Field

[0001] Embodiments of the present disclosure relate to a stage circuit, a display device including the same, and an electronic device including the same. Background Technology

[0002] With the advancement of information technology, the importance of display devices, which serve as a medium connecting users and information, is being highlighted. In response to this, the use of display devices such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs) is increasing.

[0003] The display device may include stage circuits for sequentially generating scan signals. For example, among the stage circuits, a preceding stage outputs a driving signal (e.g., a carry signal), and a succeeding stage receives the driving signal (e.g., a carry signal) output from the preceding stage and can generate a scan signal and a carry signal based thereon.

[0004] In terms of driving the display device, it is advantageous for the level of the carry signal input / output to the stage circuit to transition quickly.

[0005] In terms of the visibility of the display device, it is advantageous for the stage circuit area to be small. The problem to be solved

[0006] The technical problem to be solved is to provide a stage circuit capable of shortening the polling time of a carry signal, a display device including the same, and an electronic device including the same.

[0007] The technical problem to be solved is to provide a stage circuit capable of improving visibility, a display device including the same, and an electronic device including the same. means of solving the problem

[0008] Embodiments of the present disclosure may provide a stage circuit comprising: a first input terminal into which a clock signal is input; a second input terminal into which a driving signal is input; an output terminal for outputting a carry signal; an input unit configured to transmit a driving signal to a first node in response to a clock signal; a signal processing unit for controlling the voltages of a Q node and a QB node in response to a driving signal input to the first node; and a carry output unit comprising a boosting capacitor connected to the Q node and the output terminal, respectively, and a buffer capacitor configured to maintain the voltage of the output terminal.

[0009] The input section may include a gate electrode electrically connected to a first input terminal and a first transistor configured to switch the electrical connection between a second input terminal and a first node.

[0010] A display device according to embodiments of the present disclosure may further include a third input terminal to which a high-level voltage is input, and a fourth input terminal to which a low-level voltage is input. A signal processing unit may include a second transistor configured to switch an electrical connection between the third input terminal and QB, comprising a gate electrode electrically connected to a first node; a third transistor configured to switch an electrical connection between the first node and Q node; a fourth transistor configured to switch an electrical connection between the fourth input terminal and QB node, comprising a gate electrode electrically connected to Q node; and a stabilizing capacitor comprising a first electrode electrically connected to QB node and a second electrode electrically connected to the third input terminal.

[0011] The buffer capacitor can be directly connected to the fourth input terminal.

[0012] The second and third transistors are transistors including a P-type semiconductor, and the fourth transistor may be a transistor including an N-type semiconductor.

[0013] The third transistor may include a gate electrode electrically connected to the fourth input terminal.

[0014] The low-level voltage input to the fourth input terminal may be the first low-level voltage. The stage circuit may further include a seventh input terminal to which the second low-level voltage is input. The third transistor may include a gate electrode electrically connected to the seventh input terminal.

[0015] The second low-level voltage may be lower than the first low-level voltage.

[0016] The buffer capacitor can be directly connected to the seventh input terminal.

[0017] At least one of the second transistor, the third transistor, and the fourth transistor may be a four-terminal structure including a back gate electrode.

[0018] The output terminal may be a second output terminal. The stage circuit may further include a third input terminal to which a high-level voltage is input, a fourth input terminal to which a low-level voltage is input, a first output terminal to which a scan signal is output, and a scan output unit to which a scan signal is output according to the voltages of the Q node and the QB node. The scan output unit may include a fifth transistor configured to switch the electrical connection between the third input terminal and the first output terminal in response to the voltage of the QB node, and a sixth transistor configured to switch the electrical connection between the fourth input terminal and the first output terminal in response to the voltage of the Q node.

[0019] The fifth transistor and the sixth transistor may include a P-type semiconductor.

[0020] A display device according to embodiments of the present disclosure may further include a third input terminal to which a high-level voltage is input, and a fourth input terminal to which a low-level voltage is input. A carry output unit may further include a seventh transistor configured to switch the electrical connection between the third input terminal and the output terminal, comprising a gate electrode electrically connected to a QB node, and an eighth transistor configured to switch the electrical connection between the fourth input terminal and the output terminal, comprising a gate electrode electrically connected to a Q node.

[0021] Each of the seventh and eighth transistors may include a P-type semiconductor.

[0022] It may further include a fifth input terminal to which a reset signal is input, a sixth input terminal to which a low-level voltage is input, and a reset unit. The reset unit may include a gate electrode electrically connected to the fifth input terminal and a ninth transistor configured to switch the electrical connection between the sixth input terminal and the QB node.

[0023] Embodiments of the present disclosure may provide a display device comprising a display panel having a plurality of pixels arranged thereon and scanning lines electrically connected to the plurality of pixels arranged thereon, and a scanning driving circuit comprising a plurality of stage circuits configured to supply a scanning signal to the plurality of scanning lines, wherein at least one of the plurality of stage circuits comprises a first input terminal into which a clock signal is input, a second input terminal into which a driving signal is input, a first output terminal for outputting a scanning signal, a second output terminal for outputting a carry signal, an input unit configured to transmit a driving signal to a first node in response to the clock signal, a signal processing unit for controlling the voltage of a Q node and a QB node in response to a driving signal input to the first node, a boosting capacitor connected to the Q node and the output terminal respectively, and a buffer capacitor configured to maintain the voltage of the second output terminal, and a scanning output unit for outputting a scanning signal according to the voltage of the Q node and the QB node.

[0024] Embodiments of the present disclosure further include a third input terminal to which a high-level voltage is input and a fourth input terminal to which a low-level voltage is input, and the signal processing unit may include a second transistor configured to switch the electrical connection between the third input terminal and QB, comprising a gate electrode electrically connected to a first node; a third transistor configured to switch the electrical connection between the first node and Q node; a fourth transistor configured to switch the electrical connection between the fourth input terminal and QB node, comprising a gate electrode electrically connected to Q node; and a stabilizing capacitor comprising a first electrode electrically connected to QB node and a second electrode electrically connected to the third input terminal.

[0025] The carry output section may further include a seventh transistor configured to switch the electrical connection between a third input terminal and an output terminal, and a gate electrode electrically connected to a Q node, and an eighth transistor configured to switch the electrical connection between a fourth input terminal and an output terminal.

[0026] Embodiments of the present disclosure may provide an electronic device comprising a processor that outputs input image data, a display device that displays an image corresponding to the input image data according to a scan signal generated in a plurality of stage circuits, wherein at least one of the plurality of stage circuits comprises a first input terminal into which a clock signal is input, a second input terminal into which a driving signal is input, a first output terminal that outputs a scan signal, a second output terminal that outputs a carry signal, an input unit configured to transmit a driving signal to a first node in response to a clock signal, a signal processing unit that controls the voltage of a Q node and a QB node in response to a driving signal input to the first node, a boosting capacitor connected to the Q node and the output terminal respectively, a carry output unit including a buffer capacitor configured to maintain the voltage of the second output terminal, and a scan output unit that outputs a scan signal according to the voltage of the Q node and the QB node.

[0027] The processor can output further control signals. The display device can generate a scan control signal configured to control the driving timing of the stage circuits in response to the control signals. Effects of the invention

[0028] According to the stage circuit, display device including the same, and electronic device including the same according to the embodiments of the present disclosure, the polling time of a carry signal can be shortened.

[0029] According to the stage circuit, display device including the same, and electronic device including the same, in accordance with the embodiments of the present disclosure, visibility can be improved. Brief explanation of the drawing

[0030] FIG. 1 is a system block diagram of an electronic device according to embodiments of the present disclosure. FIG. 2 is an equivalent circuit diagram of a pixel according to one embodiment. FIG. 3 is an equivalent circuit diagram of a pixel according to another embodiment. FIG. 4 is a system block diagram of an injection driving circuit according to embodiments of the present disclosure. FIG. 5 is an equivalent circuit diagram of a stage circuit according to one embodiment. FIG. 6 is an equivalent circuit diagram of a stage circuit according to another embodiment. FIG. 7 is an equivalent circuit diagram of a stage circuit according to another embodiment. FIG. 8 is a timing diagram of a driving method of a scanning driving circuit according to one embodiment. FIG. 9 is a timing diagram of a driving method of a scanning driving circuit according to another embodiment. FIGS. 10 to 12 are drawings explaining the stage driving method of FIG. 8 with the stage circuit of FIG. 5 as the center. FIG. 13 is a timing diagram of a driving method of a scanning driving circuit according to another embodiment. FIGS. 14 to 16 are drawings explaining the stage driving method of FIG. 13 with the stage circuit of FIG. 5 as the center. FIG. 17 is an equivalent circuit diagram of a stage circuit according to another embodiment. FIG. 18 is a timing diagram of a driving method of a scanning circuit according to another embodiment. FIGS. 19 to 21 are drawings explaining the stage driving method of FIG. 18 with the stage circuit of FIG. 17 as the center. Figure 22 is a diagram comparing the polling times of the i-th carry signal and the i-th scan signal. FIG. 23 is a block diagram of an electronic device according to one embodiment. FIGS. 24 to 26 are schematic diagrams of electronic devices according to various embodiments. Specific details for implementing the invention

[0031] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0032] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are assigned to identical or similar components throughout the specification. Accordingly, the reference numerals described above may also be used in other drawings.

[0033] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thickness may be exaggerated in the drawings to clearly represent various layers and regions.

[0034] Furthermore, the expression "identical" in the explanation may mean "substantially identical." In other words, it may be an identicality to the extent that a person with ordinary knowledge would accept it as identical. Other expressions may also be those in which "substantially" has been omitted.

[0035] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0036] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Additionally, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and are explicitly defined herein unless interpreted in an ideal or overly formal sense.

[0038] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0039] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0040] FIG. 1 is a system block diagram of an electronic device (DS) according to embodiments of the present disclosure.

[0041] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110), a data driving circuit (120), a scanning driving circuit (130), a power supply circuit (150), a timing controller (140), etc.

[0042] The display panel (110) may include a substrate (SUB). The display panel (110) may include a display area (DA) where a plurality of pixels (PXL) are located on the substrate (SUB), and a non-display area (NDA) surrounding the display area (DA). A plurality of data lines (DL1 to DLm; m is an integer greater than or equal to 2) and a plurality of scan lines (SL1 to SLn; n is an integer greater than or equal to 2) electrically connected to a plurality of pixels (PXL) may be disposed on the display panel (110) (or on the display area (DA)). One or more power lines configured to apply power voltage to a plurality of pixels (PXL) may be disposed on the display panel (110). The non-display area (NDA) may be located in a peripheral area of ​​the display area (DA) (e.g., an edge area of ​​the display area (DA)). One or more pads may be located in the non-display area (NDA), and data voltage, power voltage, etc. may be supplied to multiple data lines (DL1 to DLm) through the pads.

[0043] The display panel (110) may be formed flat, but embodiments of the present disclosure are not limited thereto. For example, the display panel (110) may include curved portions formed at the left and right ends. The curved portions may have a constant curvature or a varying curvature. Additionally, the display panel (110) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0044] In one embodiment, the substrate (SUB) may comprise a rigid glass substrate. However, the embodiments of the present disclosure are not limited thereto and may comprise a flexible plastic substrate. For example, the plastic substrate may be implemented as a polyimide (PI) substrate. In another embodiment, the substrate (SUB) may be implemented as a silicon substrate.

[0045] A plurality of data lines (DL1 to DLm) may extend in one direction from the display panel (110). The one direction may be, for example, a second direction (DR2). A plurality of data lines (DL1 to DLm) may extend from the display panel (110) to the second direction (DR2) (for example, entirely to the second direction (DR2)). The second direction (DR2) may be, for example, a direction traversing from the upper side to the lower side of the display panel (110), but embodiments of the present disclosure are not limited thereto.

[0046] A plurality of scan lines (SL1 to SLn) may extend in one direction from the display panel (110). The one direction may be, for example, a first direction (DR1). A plurality of scan lines (SL1 to SLn) may extend from the display panel (110) to the first direction (DR1) (for example, to the first direction (DR1) in its entirety). The first direction (DR1) may be a direction different from the second direction (DR2), but embodiments of the present disclosure are not limited thereto. The first direction (DR1) may be, for example, a direction traversing from the left to the right of the display panel (110).

[0047] The data driving circuit (120) may be configured to supply data voltage to a plurality of data lines (DL1 to DLm). The data driving circuit (120) may generate a data voltage based on the second image data (DATA2) and the data driving circuit control signal (DCS), and output the generated data voltage to the plurality of data lines (DL1 to DLm) in time. The data driving circuit control signal (DCS) may include, for example, a source start pulse (SSP) signal, a source shift clock (SSC) signal, a source output enable (SOE) signal, etc.

[0048] The data driving circuit (120) may be implemented as an integrated circuit (e.g., a source driver integrated circuit (SDIC)) formed separately from the display panel (110), or it may be formed together with the display panel (110) and formed in at least a portion of the non-display area (NDA) of the display panel (110).

[0049] The scan driving circuit (130) is configured to output a scan signal to a plurality of scan lines (SL1 to SLn) in response to a scan driving circuit control signal (SCS). The scan driving circuit control signal (SCS) may include a start signal indicating the start of a frame, a horizontal synchronization signal for outputting a scan signal in accordance with the timing when a data voltage is applied, etc.

[0050] The scanning driving circuit (130) may be implemented as an integrated circuit (e.g., a Gate Driving Integrated Circuit (GDIC)) formed separately from the display panel (110), or it may be formed together with the display panel (110) and formed in at least a portion of the non-display area (NDA) of the display panel (110).

[0051] The power supply circuit (150) can be configured to output a constant voltage of a constant voltage level. The power supply circuit (150) can output a power voltage supplied to the display panel (110) (e.g., a first power voltage (ELVDD), a second power voltage (ELVSS), etc.). According to an embodiment, the power supply circuit (150) can output a voltage supplied to the scan driving circuit (130) (e.g., a gate high voltage, a gate low voltage, etc.). According to an embodiment, the power supply circuit (150) can output a voltage supplied to the data driving circuit (120) (e.g., a gamma voltage, etc.). The power supply circuit (150) may include, for example, a regulator (e.g., a low dropout (LDO) regulator, etc.). The power supply circuit (150) may be implemented as, for example, a power management integrated circuit (PMIC). The power supply circuit (150) may be configured to output a power voltage to power lines in response to a power supply circuit control signal (VCS).

[0052] The timing controller (140) may be configured to control the data driving circuit (120), the scanning driving circuit (130), the power supply circuit (150), etc. The timing controller (140) may generate and output control signals (DCS, SCS, VCS) for controlling the data driving circuit (120), the scanning driving circuit (130), and the power supply circuit (150) based on a control signal (CS) (e.g., a synchronization signal, a clock signal, a data enable signal, etc.) received through the host (HST). According to an embodiment, the timing controller (140) may generate a synchronization signal, a data enable signal, etc. internally based on a control signal (CS) received through the host (HST) (e.g., information regarding the driving frequency (or frame rate) of the image displayed on the display panel (110).

[0053] The timing controller (140) receives first image data (DATA1) from the host (HST) and can align the received first image data (DATA1) in pixel row units. The timing controller (140) can convert the received first image data (DATA1) according to a preset interface (e.g., Low Voltage Differential Signaling (LVDS), Display Port (DP), embedded Display Port (eDP), etc.). The second image data (DATA2) output by the timing controller (140) to the data driving circuit (120) may be converted internally by the timing controller (140) according to the preset interface.

[0054] According to an embodiment, the timing controller (140) may be placed within the display device (100) as a logic type. According to an embodiment, the timing controller (140) may be placed within the display device (100) as a processor type. The timing controller (140) may include one or more memories (e.g., registers, etc.).

[0055] The host (HST) may include a set-top box, an application processor (AP), etc. In one embodiment, the host (HST) may be a component outside the display device (100) that is not included in the display device (100). In one embodiment, the host (HST) may be mounted within the display device (100). Transmission and reception of first image data (DATA1) and a control signal (CS) may be performed between the host (HST) and the display device (100) through an interface. The interface may be, for example, a Serial Programming Interface (SPI), an Inter Integrated Circuit (I2C), a Mobile Industry Processor Interface (MIPI), etc. However, the embodiments of the present disclosure are not limited thereto.

[0056] An electronic device (DS) according to embodiments of the present disclosure may include a display device (100) and a host (HST).

[0057] In FIG. 1, the circuits supplying signals, voltages, etc. to the display panel (110) are merely classified according to their functions. For example, the data driving circuit (120) and the timing controller (140) may be formed within a single integrated circuit. The data driving circuit (120) and the timing controller (140) may be classified according to their functions within a single integrated circuit within the display device (100).

[0058] The display device (100) according to the embodiments of the present disclosure can be used as a display screen for various products such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, UMPCs (ultra-mobile personal computers), as well as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0059] FIG. 2 is an equivalent circuit diagram of a pixel (PXL) according to one embodiment.

[0060] Referring to FIG. 2, a pixel (PXL) according to embodiments of the present disclosure may include a pixel driving circuit (PXC) and a light-emitting element (LE).

[0061] The pixel driving circuit (PXC) may include two or more switching elements and one or more storage elements. In one embodiment, the switching elements may be implemented as transistors. In one embodiment, the storage elements may be implemented as capacitors.

[0062] In one embodiment, the transistor may be implemented as a bipolar junction transistor (BJT), a field effect transistor (FET), etc., but the embodiments of the present disclosure are not limited thereto.

[0063] Referring to FIG. 2, a pixel driving circuit (PXC) according to one embodiment may include first and second pixel transistors (PTR1, PTR2) and a storage capacitor (Cst1) (e.g., a first storage capacitor (Cst1)). However, depending on the embodiment, the pixel driving circuit (PXC) may include three or more transistors or two or more capacitors.

[0064] The first pixel transistor (PTR1) may include a gate electrode electrically connected to the first pixel node (PN1). The first pixel transistor (PTR1) may include a first electrode (e.g., either a source electrode or a drain electrode) electrically connected to the first power line (PL1), and a second electrode (e.g., the other of a source electrode or a drain electrode) electrically connected to the light-emitting element (LE). The first pixel transistor (PTR1) may provide a driving current to the light-emitting element (LE) corresponding to the voltage applied to the first pixel node (PN1). A first power supply voltage (ELVDD) may be applied to the first power line (PL1). The first power supply voltage (ELVDD) may be a high potential voltage.

[0065] The second pixel transistor (PTR2) may be configured to switch the electrical connection between the j-th data line (j is an integer greater than or equal to 1) and the first pixel node (PN1) in response to the i-th scan signal (SCAN[i]) (also referred to as the scan signal (SCAN[i]) below) applied to the i-th scan line (SLi) (i is an integer greater than or equal to 1). When the second pixel transistor (PTR2) is turned on in response to the scan signal (SCAN[i]) at a turn-on level (e.g., high level), a data voltage (Vdata) may be written to the pixel driving circuit (PXC). The data voltage (Vdata) or a voltage corresponding to the data voltage (Vdata) may be applied to the first pixel node (PN1).

[0066] The storage capacitor (Cst1) may include a first electrode electrically connected to a first pixel node (PN1) and a second electrode electrically connected to a second pixel node (PN2). The second pixel node (PN2) may be a node electrically connected to a first pixel transistor (PTR1) and a light-emitting element (LE). In one embodiment, the first electrode and the second electrode may be located on the same layer. In another embodiment, the first electrode and the second electrode may be located on different layers. In an embodiment where the first electrode and the second electrode are located on different layers, the first electrode and the second electrode may be located in an overlapping direction perpendicular to each other.

[0067] A light-emitting element (LE) can emit light according to a driving current flowing through a first pixel transistor (PTR1). The driving current may flow from a first power line (PL1) toward a second power line (PL2). The light-emitting element (LE) may include an anode electrode, a cathode electrode, and a light-emitting layer. The anode electrode may be electrically connected to the first power line (PL1). The cathode electrode may be electrically connected to the second power line (PL2). In one embodiment, the light-emitting layer may be located between the anode electrode and the cathode electrode. According to an embodiment, the light-emitting layer may be implemented as an organic light-emitting layer comprising an organic light-emitting material. However, embodiments of the present disclosure are not limited thereto, and the light-emitting layer may include an inorganic light-emitting material, quantum dots, nanorods, etc. Referring to FIG. 2, the anode electrode may be electrically connected to a second pixel node (PN2).

[0068] Referring to FIG. 2, a pixel driving circuit (PXC) according to embodiments of the present disclosure may include a transistor comprising at least one N-type semiconductor. For example, at least one of a first pixel transistor (PTR1) and a second pixel transistor (PTR2) may be implemented as a transistor comprising an N-type semiconductor. A transistor comprising an N-type semiconductor may be turned on in response to a high-level voltage and turned off in response to a low-level voltage.

[0069] Meanwhile, the pixel (PXL) according to the embodiments of the present disclosure is not limited to a structure having two transistors and one capacitor. According to an embodiment, the scan signal (SCAN[i]) may be applied to a signal for controlling the light emission timing of a light-emitting element (LE). According to an embodiment, the scan signal (SCAN[i]) may be applied to a signal for controlling the timing at which an initial voltage is applied to the anode electrode of the light-emitting element (LE). According to an embodiment, the scan signal (SCAN[i]) may be applied to a signal for controlling the timing at which an initial voltage is applied to the gate electrode of the first pixel transistor (PTR1). According to an embodiment, the scan signal (SCAN[i]) may be applied to a signal for controlling the timing at which a bias voltage is applied to the source electrode of the first pixel transistor (PTR1). However, the embodiments of the present disclosure are not limited thereto.

[0070] FIG. 3 is an equivalent circuit diagram of a pixel (PXL) according to another embodiment.

[0071] Referring to FIG. 3, a pixel driving circuit (PXC) according to embodiments of the present disclosure may include a first pixel transistor (PTR1), a second pixel transistor (PTR2), and a storage capacitor (Cst2).

[0072] Compared to the embodiment of FIG. 2, at least one of the first pixel transistor (PTR1) and the second pixel transistor (PTR2) may be implemented as a transistor including a P-type semiconductor. The transistor including the P-type semiconductor may be turned on in response to a low-level voltage and turned off in response to a high-level voltage.

[0073] The first pixel transistor (PTR1) may include a gate electrode electrically connected to the first pixel node (PN1). The first pixel transistor (PTR1) may include a first electrode (e.g., either a source electrode or a drain electrode) electrically connected to the first power line (PL1), and a second electrode (e.g., the other of a source electrode or a drain electrode) electrically connected to the light-emitting element (LE). The first pixel transistor (PTR1) may provide a driving current to the light-emitting element (LE) corresponding to the voltage applied to the first pixel node (PN1). A first power supply voltage (ELVDD) may be applied to the first power line (PL1). The first power supply voltage (ELVDD) may be a high potential voltage.

[0074] The second pixel transistor (PTR2) may be configured to switch the electrical connection between the j-th data line (j is an integer greater than or equal to 1) and the first pixel node (PN1) in response to a scan signal (SCAN[i]) applied to the i-th scan line (SLi) (i is an integer greater than or equal to 1). When the second pixel transistor (PTR2) is turned on in response to a scan signal (SCAN[i]) at a turn-on level (e.g., low level), a data voltage (Vdata) or a voltage corresponding to the data voltage (Vdata) may be applied to the first pixel node (PN1).

[0075] In one embodiment, a storage capacitor (Cst2) (e.g., a second storage capacitor (Cst2)) may include a first electrode electrically connected to a first pixel node (PN1) and a second electrode electrically connected to a third pixel node (PN3). The third pixel node (PN3) may be a node to which the source electrode of the first pixel transistor (PTR1) and the first power line (PL1) are connected.

[0076] FIG. 4 is a system block diagram of an injection driving circuit (130) according to embodiments of the present disclosure.

[0077] Referring to FIG. 4, the scanning driving circuit (130) according to embodiments of the present disclosure may include stage circuits (ST).

[0078] In one embodiment, the stage circuits (ST) may include first to nth stage circuits (ST1, ST2, ST3, ..., STn; hereinafter ST1 to STn).

[0079] The first to nth stage circuits (ST1 to STn) may be connected to any one of the corresponding first to nth scan lines (SL1 to SLn). The first to nth stage circuits (ST1 to STn) may output any one of the corresponding first to nth scan signals (SCAN[1], SCAN[2], SCAN[3], ..., SCAN[n]; hereinafter SCAN[1] to SCAN[n]).

[0080] The first to nth scan signals (SCAN[1] to SCAN[n]) may have a turn-on level or a turn-off level. According to an embodiment, the turn-on level may be either a high level or a low level. The turn-off level may be the other of a high level or a low level.

[0081] The scanning driving circuit (130) may be connected to a first clock line (CL1), a second clock line (CL2), and a start line (VL). A first clock signal (CLK1) may be applied to the first clock line (CL1). A second clock signal (CLK2) may be applied to the second clock line (CLK2). A start signal (VST) may be applied to the start line (VL). The first clock signal (CLK1), the second clock signal (CLK2), and the start signal (VST) may be included in a scanning driving circuit control signal (SCS).

[0082] In one embodiment, the first stage circuit (ST1) may be electrically connected to the first clock line (CL1) and the start line (VL). The first stage circuit (ST1) may output a first scan signal (SCAN[1]) to the first scan line (SL1). The first stage circuit (ST1) may output a first carry signal (CR[1]).

[0083] In one embodiment, the second stage circuit (ST2) may be electrically connected to the second clock line (CL2). The second stage circuit (ST2) may receive a first carry signal (CR[1]) from the first stage circuit (ST1). The second stage circuit (ST2) may output a second scan signal (SCAN[2]) to the second scan line (SL2). The second stage circuit (ST2) may output a second carry signal (CR[2]).

[0084] In one embodiment, the third stage circuit (ST3) may be electrically connected to the first clock line (CL1). The third stage circuit (ST3) may receive a second carry signal (CR[2]) from the second stage circuit (ST2). The third stage circuit (ST3) may output a third scan signal (SCAN[3]) to the third scan line (SL3). The third stage circuit (ST3) may output a third carry signal (CR[3]).

[0085] In one embodiment, the n-th stage circuit (STn) may be electrically connected to the second clock line (CL2). The n-th stage circuit (STn) may receive the (n-1)-th carry signal (CR[n-1]) from the (n-1)-th stage circuit. The n-th stage circuit (STn) may output the n-th scan signal (SCAN[n]) to the n-th scan line (SLn).

[0086] In one embodiment, the odd-numbered stage circuits among the first to n-th stage circuits (ST1 to STn) may be electrically connected to the first clock line (CL1). In one embodiment, the even-numbered stage circuits among the first to n-th stage circuits (ST1 to STn) may be electrically connected to the second clock line (CL2).

[0087] FIG. 5 is an equivalent circuit diagram of a stage circuit (500) according to one embodiment.

[0088] The stage circuit (500) of FIG. 5 may correspond to any one of the first to nth stage circuits (ST1 to STn) of FIG. 4.

[0089] Referring to FIG. 5, a stage circuit (500) according to embodiments of the present disclosure may include one or more input terminals, one or more output terminals, one or more switching elements, and one or more storage elements.

[0090] In one embodiment, the switching element may be implemented as a transistor. In one embodiment, the storage element may function as a capacitor.

[0091] In one embodiment, the stage circuit (500) according to the embodiments of the present disclosure may include eight transistors and three capacitors. However, the embodiments of the present disclosure are not limited thereto.

[0092] A stage circuit (500) according to embodiments of the present disclosure may include a first input terminal (501), a second input terminal (502), a third input terminal (503), and a fourth input terminal (504). The stage circuit (500) may include a first output terminal (505) and a second output terminal (506). The stage circuit (500) may include first to eighth transistors (TR1 to TR8). The stage circuit (500) may include first to third capacitors (C1 to C3).

[0093] Either one of the first clock signal (CLK1) and the second clock signal (CLK2) can be input to the first input terminal (501).

[0094] Either a start signal (VST) and a first (i-1) carry signal (CR[i-1]) may be input to the second input terminal (502). In embodiments of the present disclosure, the start signal (VST) or the first (i-1) carry signal (CR[i-1]) input to the second input terminal (502) may be referred to as a driving signal.

[0095] A high level voltage (VGH) can be input to the third input terminal (503).

[0096] A low-level voltage (VGL1) can be input to the fourth input terminal (504).

[0097] A scanning signal (SCAN[i]) can be output to the first output terminal (505).

[0098] The i-th carry signal (CR[i]) can be output to the second output terminal (506).

[0099] The first transistor (TR1) may include a gate electrode electrically connected to the first input terminal (501). The first transistor (TR1) may be configured to switch the electrical connection between the second input terminal (502) and the first node (N1) in response to a signal input to the first input terminal (501). When the first transistor (TR1) is turned on, a driving signal (e.g., a start signal (VST) or an (i-1) carry signal (CR[i-1])) may be input to the first node (N1).

[0100] The second transistor (TR2) may include a gate electrode electrically connected to the first node (N1). The second transistor (TR2) may be configured to switch the electrical connection between the third input terminal (503) and the second node (N2). When the second transistor (TR2) is turned on, a high-level voltage (VGH) may be input to the second node (N2).

[0101] The third transistor (TR3) may include a gate electrode that is electrically connected to the fourth input terminal (504). When the third transistor (TR3) is turned on, the first node (N1) and the third node (N3) may be electrically connected.

[0102] The fourth transistor (TR4) may include a gate electrode electrically connected to the third node (N3). The fourth transistor (TR4) may be configured to switch the electrical connection between the fourth input terminal (504) and the second node (N2). When the fourth transistor (TR4) is turned on, a low-level voltage (VGL1) may be input to the second node (N2).

[0103] The fifth transistor (TR5) may include a gate electrode electrically connected to the second node (N2). The fifth transistor (TR5) may be configured to switch the electrical connection between the third input terminal (503) and the first output terminal (505). When the fifth transistor (TR5) is turned on, a high level voltage (VGH) may be input to the first output terminal (505). In embodiments of the present disclosure, the second node (N2) may be referred to as the QB node. The fifth transistor (TR5) may be referred to as a scan pull-up transistor.

[0104] The sixth transistor (TR6) may include a gate electrode electrically connected to the third node (N3). The sixth transistor (TR6) may be configured to switch the electrical connection between the fourth input terminal (504) and the first output terminal (505). When the sixth transistor (TR6) is turned on, a low-level voltage (VGL1) may be input to the first output terminal (505). In embodiments of the present disclosure, the third node (N3) may be referred to as the Q node. The sixth transistor (TR6) may be referred to as a scan pull-down transistor.

[0105] The seventh transistor (TR7) may include a gate electrode electrically connected to the second node (N2). The seventh transistor (TR7) may be configured to switch the electrical connection between the third input terminal (503) and the fourth node (N4). When the seventh transistor (TR7) is turned on, a high-level voltage (VGH) may be input to the fourth node (N4). The seventh transistor may be referred to as a carry pull-up transistor.

[0106] The eighth transistor (TR8) may include a gate electrode electrically connected to the third node (N3). The eighth transistor (TR8) may be configured to switch the electrical connection between the fourth input terminal (504) and the fourth node (N4). When the eighth transistor (TR8) is turned on, a low-level voltage (VGL1) may be input to the fourth node (N4). The eighth transistor may be referred to as a carry pull-down transistor.

[0107] In one embodiment, at least one of the first to eighth transistors (TR1 to TR8) may be implemented as a transistor comprising a P-type semiconductor. In one embodiment, at least one of the first to eighth transistors (TR1 to TR8) may be implemented as a transistor comprising an N-type semiconductor.

[0108] Referring to FIG. 5, the first to third transistors (TR1 to TR3) and the fifth to eighth transistors (TR5 to TR8) may be implemented as transistors comprising a P-type semiconductor. The fourth transistor (TR4) may be implemented as a transistor comprising an N-type semiconductor. However, the embodiments of the present disclosure are not limited thereto.

[0109] The first capacitor (C1) may be configured to maintain a potential difference between the third node (N3) and the fourth node (N4). The first capacitor (C1) may include a first electrode (E11) electrically connected to the third node (N3) and a second electrode (E12) electrically connected to the fourth node (N4). The first capacitor (C1) may perform the function of lowering or raising the voltage applied to the fourth node (N4) by lowering or raising the voltage applied to the third node (N3). The first capacitor (C1) may be referred to as a boosting capacitor or may function as such.

[0110] The second capacitor (C2) may be configured to maintain the voltage applied to the second node (N2). In one embodiment, the second capacitor (C2) may include a first electrode (E21) electrically connected to the second node (N2) and a second electrode (E22) electrically connected to the third input terminal (503). The second capacitor (C2) may mitigate the problem of the driving of other transistors (e.g., the fifth transistor (TR5), the seventh transistor (TR7), etc.) being affected by the ripple voltage applied to the second node (N2). The second capacitor (C2) may be referred to as a stabilizing capacitor or may function as such.

[0111] The third capacitor (C3) may be configured to maintain the voltage applied to the fourth node (N4). In one embodiment, the third capacitor (C3) may include a first electrode (E31) electrically connected to the fourth input terminal (504) and a second electrode (E32) electrically connected to the fourth node (N4). The third capacitor (C3) can effectively lower the level of the voltage output to the second output terminal (506) by discharging during the process of lowering the voltage of the fourth node (N4). The third capacitor (C3) may be referred to as a buffer capacitor or may function as such.

[0112] In the embodiments of the present disclosure, the third capacitor (C3) may have its second electrode (E32) connected to the second output terminal (506) rather than being connected to the first output terminal (505). In the embodiments of the present disclosure, the capacitance of the third capacitor (C3) may be smaller compared to a comparative example in which the second electrode (E32) of the third capacitor (C3) is connected to the first output terminal (505). Accordingly, the voltage of the fourth node (N4) may be lowered more quickly.

[0113] The stage circuit (500) may include an input section configured to receive a (i-1) carry signal (CR[i-1]) or a start signal (VST). The input section may include a first transistor (TR1).

[0114] The stage circuit (500) may include a signal processing unit configured to control the voltage of the Q node (e.g., the third node (N3)) and the QB node (e.g., the second node (N2)). The signal processing unit may include a second transistor (TR2), a third transistor (TR3), a fourth transistor (TR4), and a second capacitor (C2). The signal processing unit may be connected to an input unit and a first node (N1).

[0115] The stage circuit (500) may include a scan output unit configured to output the i-th scan signal (SCAN[i]). The scan output unit may include a fifth transistor (TR5) and a sixth transistor (TR6). The scan output unit may be connected to a signal processing unit at a second node (N2). The scan output unit may be connected to a signal processing unit at a third node (N3).

[0116] The stage circuit (500) may include a carry output section configured to output the i-th carry signal (CR[i]). The carry output section may include a seventh transistor (TR7), an eighth transistor (TR8), a first capacitor (C1), and a third capacitor (C3). The carry output section may be connected to a signal processing section at a second node (N2). The carry output section may be connected to a signal processing section at a third node (N3).

[0117] In one embodiment, at least one of the first to eighth transistors (TR1 to TR8) may have a dual gate structure in which two sub-transistors are connected in series with each other and the gate electrodes of these sub-transistors are connected in common.

[0118] FIG. 6 is an equivalent circuit diagram of a stage circuit (600) according to another embodiment.

[0119] Compared to FIG. 5, the stage circuit (600) according to the embodiments of FIG. 6 may further include a fifth input terminal (507), a sixth input terminal (508), and a ninth transistor (TR9). The remaining components are as described in FIG. 5, and a description thereof is omitted.

[0120] A reset signal (RST) may be input to the fifth input terminal (507). In embodiments of the present disclosure, the scan drive circuit control signal (SCS) may further include a reset signal (RST). In one embodiment, the reset signal (RST) may be a signal having a turn-on level when the electronic device (DS; see FIG. 1) is turned off and then restarted.

[0121] A low-level voltage (VGL1) can be input to the 6th input terminal (508).

[0122] The ninth transistor (TR9) may include a gate electrode electrically connected to the fifth input terminal (507). The ninth transistor (TR9) may be configured to switch the electrical connection between the sixth input terminal (508) and the second node (N2). When the ninth transistor (TR9) is turned on, a low-level voltage (VGL1) may be input to the second node (N2).

[0123] In one embodiment, the ninth transistor (TR9) may be implemented as a transistor comprising a P-type semiconductor. However, the embodiments of the present disclosure are not limited thereto, and the ninth transistor (TR9) may be implemented as a transistor comprising an N-type semiconductor.

[0124] The stage circuit (500) may further include a reset unit. The reset unit may include a ninth transistor (TR9).

[0125] FIG. 7 is an equivalent circuit diagram of a stage circuit (700) according to another embodiment.

[0126] Compared to FIG. 5, the stage circuit (700) according to the embodiments of FIG. 7 may be implemented as a four-terminal structure in which one or more transistors include a gate electrode, a source electrode, a drain electrode, and a back gate electrode.

[0127] In the above embodiment, the gate electrode of the transistor can be connected to the back gate electrode. Accordingly, changes in the characteristic values ​​of the transistor (e.g., the threshold voltage, mobility, etc. of the transistor) can be mitigated.

[0128] Referring to FIG. 7, each of the first to eighth transistors (TR1 to TR8) is shown to include a back gate electrode. However, embodiments of the present disclosure are not limited thereto. For example, at least one of the first to eighth transistors (TR1 to TR8) may be implemented as a three-terminal structure that does not include a back gate electrode, and the other may be implemented as a four-terminal structure that includes a back gate electrode.

[0129] Referring further to FIG. 6, the ninth transistor (TR9) may be implemented as a three-terminal structure that does not include a back gate electrode, or as a four-terminal structure that includes a back gate electrode.

[0130] FIG. 8 is a timing diagram of a driving method (800) of a scanning driving circuit according to one embodiment.

[0131] The driving method (800) of the scanning driving circuit according to the embodiments of the present disclosure may be referred to as a driving method (800), a driving method of a display device (800), a driving method of an electronic device (800), etc.

[0132] Referring to FIG. 8, a first clock signal (CLK1), a second clock signal (CLK2), and a start signal (VST) input to a scanning driving circuit (130; refer to FIG. 4) are shown. Also, scanning signals (SCAN[1], SCAN[2], SCAN[3], ...) and carry signals (CR[1], CR[2], CR[3], ...) generated by the first clock signal (CLK1), the second clock signal (CLK2), and the start signal (VST) are shown.

[0133] Based on the first scan signal (SCAN[1]) and the first carry signal (CR[1]), a first time point (TM1a) (e.g., firsta time point (TM1a)), a second time point (TM2) (e.g., seconda time point (TM2a)), and a third time point (TM3a) (e.g., thirda time point (TM3a)) are described.

[0134] At the first time point (TM1a), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a low level (L). At the first time point (TM1a), the first scan signal (SCAN[1]) may have a low level voltage (VGL1). At the first time point (TM1a), the first carry signal (CR[1]) may have a low level voltage (VGL1).

[0135] At the second time point (TM2a), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a high level (H). At the second time point (TM2a), the first scan signal (SCAN[1]) may rise from a low level voltage (VGL1) to a high level voltage (VGH). At the second time point (TM2a), the first carry signal (CR[1]) may rise from a low level voltage (VGL1) to a high level voltage (VGH).

[0136] At the third time point (TM3a), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a low level (L). At the third time point (TM3a), the first scan signal (SCAN[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL1). At the third time point (TM3a), the first carry signal (CR[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL1).

[0137] Referring to FIG. 8, embodiments of the present disclosure may have a period during which a signal of high level voltage (VGH) is input to the first scan signal (SCAN[1]) and the second scan signal (SCAN[2]) overlap. The period during which a signal of high level voltage (VGH) is input to the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]) may not overlap.

[0138] FIG. 9 is a timing diagram of a driving method (900) of a scanning driving circuit according to another embodiment.

[0139] The driving method (900) of the scanning driving circuit according to the embodiments of the present disclosure may be referred to as the driving method (900), the driving method of the display device (900), and the driving method of the electronic device (900).

[0140] Compared to the driving method (800) according to the embodiment of FIG. 8, the driving method (900) according to the embodiment of FIG. 9 may have a longer period between the second time point (TM2a) and the third time point (TM3a). The definition of the first time point (TM1a), the second time point (TM2a), and the third time point (TM3a) is the same as that of the embodiment of FIG. 8.

[0141] Referring to FIG. 9, embodiments of the present disclosure may have a period during which a signal of high level voltage (VGH) is input to the first scan signal (SCAN[1]) and the second scan signal (SCAN[2]) overlap. The period during which a signal of high level voltage (VGH) is input to the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]) overlap.

[0142] FIGS. 10 to 12 are drawings explaining the stage driving method (800) of FIG. 8 with the stage circuit (1000a) of FIG. 5 as the center.

[0143] The stage circuit (1000a) shown in FIGS. 10 to 12 can correspond to the first stage circuit (ST1) of FIG. 4.

[0144] FIG. 10 shows the state of the stage circuit (1000a) at the first time point (TM1a) (or, the time point immediately after the first time point (TM1a)).

[0145] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (L) can be input to the first node (N1).

[0146] The second transistor (TR2) can be turned on when the first node (N1) has a low level (L). When the second transistor (TR2) is turned on, a high level voltage (VGH) can be applied to the second node (N2).

[0147] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1), and a low-level (L) start signal (VST) can be input to the first node (N1) and the third node (N3).

[0148] The fourth transistor (TR4) can be turned off by a low level (L) applied to the third node (N3).

[0149] The fifth transistor (TR5) can be turned off when the second node (N2) has a high level voltage (VGH).

[0150] The sixth transistor (TR6) can be turned on when the third node (N3) has a low level (L). When the sixth transistor (TR6) is turned on, the first output terminal (505) is electrically connected to the fourth input terminal (504) so ​​that the first scan signal (SCAN[1]) can have a low level voltage (VGL1).

[0151] The seventh transistor (TR7) can be turned off when the second node (N2) has a high level voltage (VGH).

[0152] The eighth transistor (TR8) can be turned on when the third node (N3) has a low level (L). When the eighth transistor (TR8) is turned on, the fourth node (N4) is electrically connected to the fourth input terminal (504) so ​​that the first carry signal (CR[1]) can have a low level voltage (VGL1).

[0153] FIG. 11 shows the state of the stage circuit (1000a) at the second time point (TM2a) (or, the time point immediately after the second time point (TM2a)).

[0154] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a high level (H) can be input to the first node (N1).

[0155] The second transistor (TR2) can be turned off when the first node (N1) has a high level (H). When the second transistor (TR2) is turned off, the second node (N2) can be electrically isolated from the third input terminal (503).

[0156] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1) so that a high-level (H) start signal (VST) can be input.

[0157] The fourth transistor (TR4) can be turned on when the third node (N3) has a high level (H). When the fourth transistor (TR4) is turned on, the second node (N2) can be electrically connected to the fourth input terminal (504). A low level voltage (VGL1) can be applied to the second node (N2).

[0158] The fifth transistor (TR5) can be turned on when the second node (N2) has a low level voltage (VGL1). When the fifth transistor (TR5) is turned on, the first output terminal (505) can be electrically connected to the third input terminal (503). The first scan signal (SCAN[1]) can have a high level voltage (VGH).

[0159] The sixth transistor (TR6) can be turned off when the third node (N3) has a high level (H). When the sixth transistor (TR6) is turned off, the first output terminal (505) can be electrically isolated from the fourth input terminal (504).

[0160] The seventh transistor (TR7) can be turned on when the second node (N2) has a low level voltage (VGL1). When the seventh transistor (TR7) is turned on, the third input terminal (503) can be electrically connected to the fourth node (N4). A high level voltage (VGH) can be applied to the fourth node (N4). The first carry signal (CR[1]) can have a high level voltage (VGH).

[0161] The eighth transistor (TR8) can be turned off when the third node (N3) has a high level (H). When the eighth transistor (TR8) is turned off, the fourth node (N4) can be electrically isolated from the fourth input terminal (504).

[0162] Accordingly, the first scan signal (SCAN[1]) and the first carry signal (CR[1]) can rise from a low level voltage (VGL1) to a high level voltage (VGH).

[0163] FIG. 12 shows the state of the stage circuit (1000a) at the third time point (TM3a) (or, the time point immediately after the third time point (TM3a)).

[0164] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) at a low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (L) can be input to the first node (N1). The voltage of the first node (N1) can drop from a high level (H) to a low level (L).

[0165] The second transistor (TR2) can be turned on when the first node (N1) has a low level (L). When the second transistor (TR2) is turned on, a high level voltage (VGH) can be applied to the second node (N2). The voltage of the second node (N2) can rise from the low level voltage (VGL1) to the high level voltage (VGH).

[0166] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1) so that a low-level (L) start signal (VST) can be input. The voltage of the third node (N3) can drop from a high level (H) to a low level (L).

[0167] The fourth transistor (TR4) can be turned off when the third node (N3) has a low level (L). As the fourth transistor (TR4) is turned off, the electrical connection between the second node (N2) and the fourth input terminal (504) can be isolated.

[0168] The fifth transistor (TR5) can be turned off when the second node (N2) has a high level voltage (VGH). As the fifth transistor (TR5) is turned off, the electrical connection between the first output terminal (505) and the third input terminal (503) can be isolated.

[0169] The sixth transistor (TR6) can be turned on when the third node (N3) has a low level (L). When the sixth transistor (TR6) is turned on, the first output terminal (505) is electrically connected to the fourth input terminal (504) so ​​that the first scan signal (SCAN[1]) can have a low level voltage (VGL1).

[0170] The seventh transistor (TR7) can be turned off when the second node (N2) has a high level voltage (VGH). As the seventh transistor (TR7) is turned off, the electrical connection between the second output terminal (506) and the third input terminal (503) can be isolated.

[0171] The eighth transistor (TR8) can be turned on when the third node (N3) has a low level (L). When the eighth transistor (TR8) is turned on, the fourth node (N4) is electrically connected to the fourth input terminal (504) so ​​that the first carry signal (CR[1]) can have a low level voltage (VGL1).

[0172] Accordingly, the first scan signal (SCAN[1]) and the first carry signal (CR[1]) can be lowered from a high level voltage (VGH) to a low level voltage (VGL1).

[0173] Meanwhile, at the third time point (TM3), the voltage of the second electrode (E32) of the third capacitor (C3) drops from a high level voltage (VGH) to a low level voltage (VGL1). Embodiments of the present disclosure can lower the voltage of the fourth node (N4) quickly by making the capacitance of the third capacitor (C3) relatively small. This allows the voltage of the first carry signal (CR[1]) to drop more quickly.

[0174] FIG. 13 is a timing diagram of a driving method (1300) of a scanning driving circuit according to another embodiment.

[0175] The driving method (1300) of the scanning driving circuit according to the embodiments of the present disclosure may be referred to as the driving method (1300), the driving method of the display device (1300), and the driving method of the electronic device (1300).

[0176] Referring to FIG. 13, a first clock signal (CLK1), a second clock signal (CLK2), and a start signal (VST) input to a scanning driving circuit (130; refer to FIG. 4) are shown. Also, scanning signals (SCAN[1], SCAN[2], SCAN[3], ...) and carry signals (CR[1], CR[2], CR[3], ...) generated by the first clock signal (CLK1), the second clock signal (CLK2), and the start signal (VST) are shown.

[0177] Based on the first scan signal (SCAN[1]) and the first carry signal (CR[1]), a first time point (TM1b) (e.g., first time point 1b (TM1b)), a second time point (TM2b) (e.g., second time point 2b (TM2b)), and a third time point (TM3b) (e.g., third time point 3b (TM3b)) are described.

[0178] At the first time point (TM1b), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a high level (H). At the first time point (TM1b), the first scan signal (SCAN[1]) may have a high level voltage (VGH). At the first time point (TM1b), the first carry signal (CR[1]) may have a high level voltage (VGH).

[0179] At the second time point (TM2b), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a low level (L). At the second time point (TM2b), the first scan signal (SCAN[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL1). At the second time point (TM2b), the first carry signal (CR[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL1).

[0180] At the third time point (TM3b), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a high level (H). At the third time point (TM3b), the first scan signal (SCAN[1]) may rise from a low level voltage (VGL1) to a high level voltage (VGH). At the third time point (TM3b), the first carry signal (CR[1]) may rise from a low level voltage (VGL1) to a high level voltage (VGH).

[0181] Referring to FIG. 13, embodiments of the present disclosure may have overlapping periods during which a signal of low level voltage (VGL1) is input to the first scan signal (SCAN[1]) and the second scan signal (SCAN[2]). The periods during which a signal of low level voltage (VGL1) is input to the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]) may not overlap.

[0182] FIGS. 14 to 16 are drawings explaining the stage driving method (1300a) of FIG. 13 with the stage circuit (1400a) of FIG. 5 as the center.

[0183] The stage circuit (1400a) shown in FIGS. 14 to 16 can correspond to the first stage circuit (ST1) of FIG. 4.

[0184] FIG. 14 shows the state of the stage circuit (1400a) at the first time point (TM1b) (or, the time point immediately after the first time point (TM1b)).

[0185] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (L) can be input to the first node (N1).

[0186] The second transistor (TR2) can be turned off when the first node (N1) has a high level (H). When the second transistor (TR2) is turned off, the second node (N2) and the third input terminal (503) can be electrically isolated.

[0187] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1), and a high-level (H) start signal (VST) can be input to the first node (N1) and the third node (N3).

[0188] The fourth transistor (TR4) can be turned on in response to a high-level (H) signal applied to the third node (N3). The second node (N2) is electrically connected to the fourth input terminal (504), and a low-level voltage (VGL1) can be applied to the second node (N2).

[0189] The fifth transistor (TR5) can be turned on in response to a low-level voltage (VGL1) applied to the second node (N2).

[0190] The sixth transistor (TR6) can be turned off when the third node (N3) has a high level (H). When the sixth transistor (TR6) is turned off, the first output terminal (505) can be electrically isolated from the fourth input terminal (504).

[0191] The seventh transistor (TR7) can be turned on when the second node (N2) has a low level voltage (VGL1).

[0192] The eighth transistor (TR8) can be turned off when the third node (N3) has a high level (H). When the eighth transistor (TR8) is turned off, the fourth node (N4) can be electrically isolated from the fourth input terminal (504).

[0193] FIG. 15 shows the state of the stage circuit (1400a) at the second time point (TM2b) (or, the time point immediately after the second time point (TM2b)).

[0194] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (HL) can be input to the first node (N1).

[0195] The second transistor (TR2) can be turned on when the first node (N1) has a low level (L). When the second transistor (TR2) is turned on, the second node (N2) is electrically connected to the third input terminal (503), and a high level voltage (VGH) can be applied to the second node (N2).

[0196] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1), so that the first node (N1) and the third node (N3) can receive a low-level (L) start signal (VST).

[0197] The fourth transistor (TR4) can be turned on when the third node (N3) has a high level (H). When the fourth transistor (TR4) is turned on, the second node (N2) can be electrically connected to the fourth input terminal (504). A low level voltage (VGL1) can be applied to the second node (N2).

[0198] The fifth transistor (TR5) can be turned off when the second node (N2) has a high level voltage (VGH). When the fifth transistor (TR5) is turned off, the first output terminal (505) can be electrically isolated from the third input terminal (503).

[0199] The sixth transistor (TR6) can be turned on when the third node (N3) has a low level (L). When the sixth transistor (TR6) is turned on, the first output terminal (505) can be electrically connected to the fourth input terminal (504). The first scan signal (SCAN[1]) can have a low level voltage (VGL1).

[0200] The seventh transistor (TR7) can be turned off when the second node (N2) has a high level voltage (VGH). When the seventh transistor (TR7) is turned off, the third input terminal (503) can be electrically isolated from the fourth node (N4).

[0201] The eighth transistor (TR8) can be turned on when the third node (N3) has a low level (L). When the eighth transistor (TR8) is turned on, the fourth node (N4) can be electrically connected to the fourth input terminal (504). The first carry signal (CR[1]) can have a low level voltage (VGL1).

[0202] Accordingly, the first scan signal (SCAN[1]) and the first carry signal (CR[1]) can be lowered from a high level voltage (VGH) to a low level voltage (VGL1).

[0203] Meanwhile, at the second time point (TM2b), the voltage of the second electrode (E32) of the third capacitor (C3) drops from a high level voltage (VGH) to a low level voltage (VGL1). Embodiments of the present disclosure can lower the voltage of the fourth node (N4) quickly by making the capacitance of the third capacitor (C3) relatively small. This allows the voltage of the first carry signal (CR[1]) to drop more quickly.

[0204] FIG. 16 shows the state of the stage circuit (1400a) at the third time point (TM3b) (or, the time point immediately after the third time point (TM3b)).

[0205] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) at a low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a high level (H) can be input to the first node (N1). The voltage of the first node (N1) can rise from a low level (L) to a high level (H).

[0206] The second transistor (TR2) can be turned off when the first node (N1) has a high level (H). When the second transistor (TR2) is turned off, the second node (N2) and the third input terminal (503) can be electrically isolated.

[0207] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1) so that a high-level (H) start signal (VST) can be input. The voltage of the third node (N3) can rise from a low level (L) to a high level (H).

[0208] The fourth transistor (TR4) can be turned on when the third node (N3) has a high level (H). As the fourth transistor (TR4) is turned on, the second node (N2) and the fourth input terminal (504) can be electrically connected. The voltage of the second node (N2) can drop from a high level voltage (VGH) to a low level voltage (VGL1).

[0209] The fifth transistor (TR5) can be turned on when the second node (N2) has a low level voltage (VGL1). When the fifth transistor (TR5) is turned on, the first output terminal (505) can be electrically connected to the third input terminal (503). The first scan signal (SCAN[1]) can rise from the low level voltage (VGL1) to the high level voltage (VGH).

[0210] The sixth transistor (TR6) can be turned off when the third node (N3) has a high level (H). When the sixth transistor (TR6) is turned off, the first output terminal (505) can be electrically isolated from the fourth input terminal (504).

[0211] The seventh transistor (TR7) can be turned on when the second node (N2) has a low level voltage (VGL1). When the seventh transistor (TR7) is turned on, the second output terminal (506) can be electrically connected to the third input terminal (503). The first carry signal (CR[1]) can rise from the low level voltage (VGL1) to the high level voltage (VGH).

[0212] The eighth transistor (TR8) can be turned off when the third node (N3) has a high level (H). When the eighth transistor (TR8) is turned off, the fourth node (N4) can be electrically isolated from the fourth input terminal (504).

[0213] Accordingly, the first scan signal (SCAN[1]) and the first carry signal (CR[1]) can rise from a low level voltage (VGL1) to a high level voltage (VGH).

[0214] FIG. 17 is an equivalent circuit diagram of a stage circuit (1700) according to another embodiment.

[0215] The stage circuit (1700) of FIG. 17 may correspond to any one of the first to nth stage circuits (ST1 to STn) of FIG. 4.

[0216] Referring to FIG. 17, a stage circuit (1700) according to embodiments of the present disclosure may include one or more input terminals, one or more output terminals, one or more switching elements, and one or more storage elements.

[0217] In one embodiment, the switching element may be implemented as a transistor. In one embodiment, the storage element may function as a capacitor.

[0218] In one embodiment, the stage circuit (1700) according to the embodiments of the present disclosure may include eight transistors and three capacitors. However, the embodiments of the present disclosure are not limited thereto.

[0219] A stage circuit (1700) according to embodiments of the present disclosure may include a first input terminal (1701), a second input terminal (1702), a third input terminal (1703), a fourth input terminal (1704), and a seventh input terminal (1707). The stage circuit (1700) may include a first output terminal (1705) and a second output terminal (1706). The stage circuit (1700) may include first to eighth transistors (TR1 to TR8). The stage circuit (1700) may include first to third capacitors (C1 to C3).

[0220] Either one of the first clock signal (CLK1) and the second clock signal (CLK2) can be input to the first input terminal (1701).

[0221] Either a start signal (VST) and a (i-1) carry signal (CR[i-1]) can be input to the second input terminal (1702).

[0222] A high level voltage (VGH) can be input to the third input terminal (1703).

[0223] A low-level voltage (VGL1) (e.g., a first low-level voltage (VGL1)) can be input to the fourth input terminal (1704).

[0224] A low-level voltage (VGL2) (e.g., a second low-level voltage (VGL2)) can be input to the seventh input terminal (1707).

[0225] A scan signal (SCAN[i]) can be output to the first output terminal (1705).

[0226] The i-th carry signal (CR[i]) can be output to the second output terminal (1706).

[0227] The first transistor (TR1) may include a gate electrode electrically connected to the first input terminal (1701). The first transistor (TR1) may be configured to switch the electrical connection between the second input terminal (1702) and the first node (N1) in response to a signal input to the first input terminal (1701). When the first transistor (TR1) is turned on, a start signal (VST) or a (i-1) carry signal (CR[i-1]) may be input to the first node (N1).

[0228] The second transistor (TR2) may include a gate electrode electrically connected to the first node (N1). The second transistor (TR2) may be configured to switch the electrical connection between the third input terminal (1703) and the second node (N2). When the second transistor (TR2) is turned on, a high-level voltage (VGH) may be input to the second node (N2).

[0229] The third transistor (TR3) may include a gate electrode electrically connected to the seventh input terminal (1705). When the third transistor (TR3) is turned on, the first node (N1) and the third node (N3) may be electrically connected.

[0230] The fourth transistor (TR4) may include a gate electrode electrically connected to the third node (N3). The fourth transistor (TR4) may be configured to switch the electrical connection between the fourth input terminal (1704) and the second node (N2). When the fourth transistor (TR4) is turned on, a low-level voltage (VGL1) may be input to the second node (N2).

[0231] The fifth transistor (TR5) may include a gate electrode electrically connected to the second node (N2). The fifth transistor (TR5) may be configured to switch the electrical connection between the third input terminal (1703) and the first output terminal (1705). When the fifth transistor (TR5) is turned on, a high-level voltage (VGH) may be input to the first output terminal (1705). In embodiments of the present disclosure, the second node (N2) may be referred to as the QB node.

[0232] The sixth transistor (TR6) may include a gate electrode electrically connected to the third node (N3). The sixth transistor (TR6) may be configured to switch the electrical connection between the fourth input terminal (1704) and the first output terminal (1705). When the sixth transistor (TR6) is turned on, a low-level voltage (VGL1) may be input to the first output terminal (1705). In embodiments of the present disclosure, the third node (N3) may be referred to as the Q node.

[0233] The seventh transistor (TR7) may include a gate electrode electrically connected to the second node (N2). The seventh transistor (TR7) may be configured to switch the electrical connection between the third input terminal (1703) and the fourth node (N4). When the seventh transistor (TR7) is turned on, a high-level voltage (VGH) may be input to the fourth node (N4).

[0234] The eighth transistor (TR8) may include a gate electrode electrically connected to the third node (N3). The eighth transistor (TR8) may be configured to switch the electrical connection between the seventh input terminal (1707) and the fourth node (N4). When the eighth transistor (TR8) is turned on, a low-level voltage (VGL2) may be input to the fourth node (N4).

[0235] In one embodiment, at least one of the first to eighth transistors (TR1 to TR8) may be implemented as a transistor comprising a P-type semiconductor. In one embodiment, at least one of the first to eighth transistors (TR1 to TR8) may be implemented as a transistor comprising an N-type semiconductor.

[0236] Referring to FIG. 5, the first to third transistors (TR1 to TR3) and the fifth to eighth transistors (TR5 to TR8) may be implemented as transistors comprising a P-type semiconductor. The fourth transistor (TR4) may be implemented as a transistor comprising an N-type semiconductor. However, the embodiments of the present disclosure are not limited thereto.

[0237] The first capacitor (C1) may be configured to maintain a potential difference between the third node (N3) and the fourth node (N4). The first capacitor (C1) may include a first electrode (E11) electrically connected to the third node (N3) and a second electrode (E12) electrically connected to the fourth node (N4). The first capacitor (C1) may perform the function of lowering or raising the voltage applied to the fourth node (N4) by lowering or raising the voltage applied to the third node (N3). The first capacitor (C1) may be referred to as a boosting capacitor or may function as such.

[0238] The second capacitor (C2) may be configured to maintain the voltage applied to the second node (N2). In one embodiment, the second capacitor (C2) may include a first electrode (E21) electrically connected to the second node (N2) and a second electrode (E22) electrically connected to the third input terminal (503). The second capacitor (C2) may mitigate the problem of the driving of other transistors (e.g., the fifth transistor (TR5), the seventh transistor (TR7), etc.) being affected by the ripple voltage applied to the second node (N2). The second capacitor (C2) may be referred to as a stabilizing capacitor or may function as such.

[0239] The third capacitor (C3) may be configured to maintain the voltage applied to the fourth node (N4). In one embodiment, the third capacitor (C3) may include a first electrode (E31) electrically connected to the seventh input terminal (1707) and a second electrode (E32) electrically connected to the fourth node (N4). The third capacitor (C3) can effectively lower the level of the voltage output from the second output terminal (1706) by discharging during the process of lowering the voltage of the fourth node (N4). The third capacitor (C3) may be referred to as a buffer capacitor or may function as such.

[0240] In the embodiments of the present disclosure, the third capacitor (C3) may have its second electrode (E32) connected to the second output terminal (1706) rather than being connected to the first output terminal (1705). In the embodiments of the present disclosure, the capacitance of the third capacitor (C3) may be smaller compared to a comparative example in which the second electrode (E32) of the third capacitor (C3) is connected to the first output terminal (1705). Accordingly, the voltage of the fourth node (N4) may be lowered more quickly.

[0241] Meanwhile, in embodiments of the present disclosure, the low-level voltage (VGL2) (e.g., the second low-level voltage (VGL2)) applied to the seventh input terminal (1707) may be lower than the low-level voltage (VGL1) (e.g., the first low-level voltage (VGL1)) applied to the fourth input terminal (1704). Compared to the embodiment of FIG. 5, the level of the constant voltage applied to the first electrode (E31) of the third capacitor (C3) is lowered, so that the third capacitor (C3) can be discharged more effectively when the i-th carry signal (CR[i]) transitions from a high level to a low level. This allows the length of the period during which the i-th carry signal (CR[i]) transitions from a high level to a low level to be reduced further.

[0242] FIG. 18 is a timing diagram of a driving method (1800) of a scanning circuit according to another embodiment.

[0243] The driving method (1800) of the scanning driving circuit according to the embodiments of the present disclosure may be referred to as a driving method (1800), a driving method of a display device (1800), a driving method of an electronic device (1800), etc.

[0244] Referring to FIG. 18, a first clock signal (CLK1), a second clock signal (CLK2), and a start signal (VST) input to a scanning driving circuit (130; refer to FIG. 4) are shown. Also, scanning signals (SCAN[1], SCAN[2], SCAN[3], ...) and carry signals (CR[1], CR[2], CR[3], ...) generated by the first clock signal (CLK1), the second clock signal (CLK2), and the start signal (VST) are shown.

[0245] Based on the first scan signal (SCAN[1]) and the first carry signal (CR[1]), a first time point (TM1c) (e.g., the first time point (TM1c)), a second time point (TM2c) (e.g., the second time point (TM2c)), and a third time point (TM3c) (e.g., the third time point (TM3c)) are described.

[0246] At the first time point (TM1c), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a low level (L). At the first time point (TM1c), the first scan signal (SCAN[1]) may have a low level voltage (VGL1). At the first time point (TM1c), the first carry signal (CR[1]) may have a low level voltage (VGL2).

[0247] At the second time point (TM2c), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a high level (H). At the second time point (TM2c), the first scan signal (SCAN[1]) may rise from a low level voltage (VGL1) to a high level voltage (VGH). At the second time point (TM2c), the first carry signal (CR[1]) may rise from a low level voltage (VGL2) to a high level voltage (VGH).

[0248] At the third time point (TM3c), the first clock signal (CLK1) transitions from a high level (H) to a low level (L), and the start signal (VST) may have a low level (L). At the third time point (TM3c), the first scan signal (SCAN[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL1). At the third time point (TM3c), the first carry signal (CR[1]) may drop from a high level voltage (VGH) to a low level voltage (VGL2).

[0249] Referring to FIG. 18, embodiments of the present disclosure may have overlapping periods during which a signal of high level voltage (VGH) is input between the first scan signal (SCAN[1]) and the second scan signal (SCAN[2]). The periods during which a signal of high level voltage (VGH) is input between the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]) may not overlap. However, embodiments of the present disclosure are not limited thereto. For example, with reference to the embodiment of FIG. 9, the periods during which a signal of high level voltage (VGH) is input between the first scan signal (SCAN[1]) and the third scan signal (SCAN[3]) may overlap by varying the length of the period between the second time point (TM2c) and the third time point (TM3c).

[0250] FIGS. 19 to 21 are drawings explaining the stage driving method (1800a) of FIG. 18 with the stage circuit of FIG. 17 as the center.

[0251] The stage circuit (1900a) shown in FIGS. 19 to 21 can correspond to the first stage circuit (ST1) of FIG. 4.

[0252] FIG. 19 shows the state of the stage circuit (1900a) at the first time point (TM1c) (or, the time point immediately after the first time point (TM1c)).

[0253] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (L) can be input to the first node (N1).

[0254] The second transistor (TR2) can be turned on when the first node (N1) has a low level (L). When the second transistor (TR2) is turned on, a high level voltage (VGH) can be applied to the second node (N2).

[0255] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL2). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1), and a low-level (L) start signal (VST) can be input to the first node (N1) and the third node (N3).

[0256] The fourth transistor (TR4) can be turned off by a low level (L) applied to the third node (N3).

[0257] The fifth transistor (TR5) can be turned off when the second node (N2) has a high level voltage (VGH).

[0258] The sixth transistor (TR6) can be turned on when the third node (N3) has a low level (L). When the sixth transistor (TR6) is turned on, the first output terminal (1705) is electrically connected to the fourth input terminal (1704) so ​​that the first scan signal (SCAN[1]) can have a low level voltage (VGL1).

[0259] The seventh transistor (TR7) can be turned off when the second node (N2) has a high level voltage (VGH).

[0260] The eighth transistor (TR8) can be turned on when the third node (N3) has a low level (L). When the eighth transistor (TR8) is turned on, the fourth node (N4) is electrically connected to the seventh input terminal (1707) so that the first carry signal (CR[1]) can have a low level voltage (VGL2).

[0261] FIG. 20 shows the state of the stage circuit (1900a) at the second time point (TM2c) (or, the time point immediately after the second time point (TM2c)).

[0262] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) of low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a high level (H) can be input to the first node (N1).

[0263] The second transistor (TR2) can be turned off when the first node (N1) has a high level (H). When the second transistor (TR2) is turned off, the second node (N2) can be electrically isolated from the third input terminal (1703).

[0264] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL1). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1) so that a high-level (H) start signal (VST) can be input.

[0265] The fourth transistor (TR4) can be turned on when the third node (N3) has a high level (H). When the fourth transistor (TR4) is turned on, the second node (N2) can be electrically connected to the fourth input terminal (1704). A low level voltage (VGL1) can be applied to the second node (N2).

[0266] The fifth transistor (TR5) can be turned on when the second node (N2) has a low level voltage (VGL1). When the fifth transistor (TR5) is turned on, the first output terminal (1705) can be electrically connected to the third input terminal (1703). The first scan signal (SCAN[1]) can have a high level voltage (VGH).

[0267] The sixth transistor (TR6) can be turned off when the third node (N3) has a high level (H). When the sixth transistor (TR6) is turned off, the first output terminal (1705) can be electrically isolated from the fourth input terminal (1704).

[0268] The seventh transistor (TR7) can be turned on when the second node (N2) has a low level voltage (VGL1). When the seventh transistor (TR7) is turned on, the third input terminal (1703) can be electrically connected to the fourth node (N4). A high level voltage (VGH) can be applied to the fourth node (N4). The first carry signal (CR[1]) can have a high level voltage (VGH).

[0269] The eighth transistor (TR8) can be turned off when the third node (N3) has a high level (H). When the eighth transistor (TR8) is turned off, the fourth node (N4) can be electrically isolated from the fourth input terminal (1704).

[0270] Accordingly, the first scan signal (SCAN[1]) can rise from a low level voltage (VGL1) to a high level voltage (VGH). The first carry signal (CR[1]) can rise from a low level voltage (VGL2) to a high level voltage (VGH).

[0271] FIG. 21 shows the state of the stage circuit (1900a) at the third time point (TM3c) (or, the time point immediately after the third time point (TM3c)).

[0272] The first transistor (TR1) can be turned on in response to a first clock signal (CLK1) at a low level (L). When the first transistor (TR1) is turned on, a start signal (VST) having a low level (L) can be input to the first node (N1). The voltage of the first node (N1) can drop from a high level (H) to a low level (L).

[0273] The second transistor (TR2) can be turned on when the first node (N1) has a low level (L). When the second transistor (TR2) is turned on, a high level voltage (VGH) can be applied to the second node (N2). The voltage of the second node (N2) can rise from the low level voltage (VGL1) to the high level voltage (VGH).

[0274] The third transistor (TR3) can be turned on in response to a low-level voltage (VGL2). When the third transistor (TR3) is turned on, the third node (N3) is electrically connected to the first node (N1) so that a low-level (L) start signal (VST) can be input. The voltage of the third node (N3) can drop from a high level (H) to a low level (L).

[0275] The fourth transistor (TR4) can be turned off when the third node (N3) has a low level (L). As the fourth transistor (TR4) is turned off, the electrical connection between the second node (N2) and the fourth input terminal (504) can be isolated.

[0276] The fifth transistor (TR5) can be turned off when the second node (N2) has a high level voltage (VGH). As the fifth transistor (TR5) is turned off, the electrical connection between the first output terminal (1705) and the third input terminal (1703) can be isolated.

[0277] The sixth transistor (TR6) can be turned on when the third node (N3) has a low level (L). When the sixth transistor (TR6) is turned on, the first output terminal (1705) is electrically connected to the fourth input terminal (1704) so ​​that the first scan signal (SCAN[1]) can have a low level voltage (VGL1).

[0278] The seventh transistor (TR7) can be turned off when the second node (N2) has a high level voltage (VGH). As the seventh transistor (TR7) is turned off, the electrical connection between the second output terminal (1706) and the third input terminal (1703) can be isolated.

[0279] The eighth transistor (TR8) can be turned on when the third node (N3) has a low level (L). When the eighth transistor (TR8) is turned on, the fourth node (N4) is electrically connected to the seventh input terminal (1707) so that the first carry signal (CR[1]) can have a low level voltage (VGL2).

[0280] Accordingly, the first scan signal (SCAN[1]) can be lowered from a high level voltage (VGH) to a low level voltage (VGL1). The first carry signal (CR[1]) can be lowered from a high level voltage (VGH) to a low level voltage (VGL2).

[0281] Meanwhile, at the third time point (TM3c), the voltage of the second electrode (E32) of the third capacitor (C3) drops from a high level voltage (VGH) to a low level voltage (VGL2). Embodiments of the present disclosure can lower the voltage of the fourth node (N4) quickly by making the capacitance of the third capacitor (C3) relatively small. This allows the voltage of the first carry signal (CR[1]) to drop more quickly.

[0282] Figure 22 is a diagram comparing the polling times of the i-th carry signal (CR[i]) and the i-th scan signal (SCAN[i]).

[0283] Referring to FIG. 22, in embodiments of the present disclosure, the polling time (FLT1) during which the i-th carry signal (CR[i]) falls from a high level voltage (VGH) to a low level voltage (VGL1 or VGL2) is smaller than the polling time (FLT2) during which the i-th scan signal (SCAN[i]) falls from a high level voltage (VGH) to a low level voltage (VGL1).

[0284] According to embodiments of the present disclosure, the area of ​​the non-display area (NDA; see FIG. 1) can be reduced overall by reducing the area for providing the third capacitor (C3; see FIG. 5, etc.).

[0285] According to embodiments of the present disclosure, the reliability of the scanning drive circuit (130; see FIG. 1) can be improved as the polling time (FLT1) of the i-th carry signal (CR[i]) is shortened.

[0286] A display device (100; see FIG. 1) according to an embodiment can be applied to various electronic devices (DS; see FIG. 1). An electronic device according to one embodiment includes the display device described above and may further include a module or device having additional functions other than the display device.

[0287] FIG. 23 is a block diagram of an electronic device (2300) according to one embodiment.

[0288] The electronic device (2300) according to the embodiment of FIG. 23 may include the electronic device (DS; see FIG. 1) of FIG. 1 described above.

[0289] Referring to FIG. 23, an electronic device (2300) according to one embodiment may include a display module (2310), a processor (2320), a memory (2330), and a power module (2340).

[0290] The display module (2310) may include the display device (100) of FIG. 1 described above.

[0291] The processor (2320) may include at least one of a Central Processing Unit (CPU), an Application Processor (AP), a Graphics Processing Unit (GPU), a Communication Processor (CP), an Image Signal Processor (ISP), and a controller. In one embodiment, the processor (2320) may be provided divided into two or more parts from a functional or structural perspective. For example, the processor (2320) may include a main processor in the form of a first driving chip including a central processing unit, and an auxiliary process in the form of a second driving chip including a controller that receives a video signal from the main processor and processes the video signal to match the interface specifications of the display module (2310). The processor (2320) may include the host (HST) of FIG. 1 described above.

[0292] The memory (2330) may include at least one of non-volatile memory and volatile memory. Data information necessary for the operation of the processor (2320) or the display module (2310) may be stored in the memory (2330). When the processor (2320) executes an application stored in the memory (2330), an image data signal and / or an input control signal is transmitted to the display module (2310), and the display module (2310) can process the received signal and output image information through a display screen.

[0293] The power module (2340) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (2300). Power conversion by the power conversion module may include, but is not limited to, DC (Direct Current)-DC conversion, AC (Alternating Current)-DC conversion, and DC-AC conversion.

[0294] The electronic device (2300) may further include an input module (2350), an output module (2360), and / or a communication module (2370).

[0295] The input module (2350) can provide input information to the processor (2320) and / or the display module (2310). The input module (2350) may include physical buttons, a keyboard, a microphone, as well as various sensor modules. Examples of sensor modules may include touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors, light receiving sensors, photoelectric conversion sensors, temperature sensors, as well as biosensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and heart rate sensors.

[0296] The output module (2360) can receive information other than the image received from the processor (2320) and provide it to the user. For example, the output module (2360) may be a non-image output module. Examples of non-image output modules include sound modules, haptic modules, light-emitting modules, etc., and may include other functional modules unique to electronic devices (e.g., a cooling module of a refrigerator).

[0297] The communication module (2370) is a module responsible for transmitting and receiving information between the electronic device (2300) and an external device, and may include a receiving unit and a transmitting unit. The communication module (2370) may include various wireless communication modules such as a mobile communication module, a Wi-Fi module, a Bluetooth module, or various wired communication modules.

[0298] At least one of each component of the electronic device (2300) described above may be included within the display device according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include a display module (2310), and the processor (2320), memory (2330), and power module (2340) may be provided in the form of other devices within the electronic device (2300) other than the display device. As another example, the power module (2340) may be provided within the display device and may supply power to the processor (2320) and memory (2330) provided within the electronic device (2300) other than the display device, but is not limited to the above examples.

[0299] FIGS. 24 to 26 are schematic diagrams of an electronic device (2300; see FIG. 23) according to various embodiments.

[0300] FIGS. 24 to 26 illustrate examples of various electronic devices to which a display device according to embodiments is applied.

[0301] FIG. 24 illustrates examples of electronic devices, including a smartphone (2300_1a), a tablet PC (2300_1b), a laptop (2300_1c), a TV (2300_1d), and a desktop monitor (2300_1e).

[0302] A smartphone (2300_1a) may include an input module (2350; see FIG. 23), such as a touch sensor, and a communication module (2370; see FIG. 23), in addition to a display module (2310; see FIG. 23). The smartphone (2300_1a) can process information received through the communication module (2370) or other input modules (2350) and display information through the display module (2310) of the display device.

[0303] In the case of a tablet PC (2300_1b), laptop (2300_1c), TV (Television) (2300_1d), and desktop monitor (2300_1e), it also includes a display module (2310; see FIG. 23) and an input module (2350; see FIG. 23), similar to a smartphone (2300_1a), and may additionally include a communication module (2370; see FIG. 23) in some cases.

[0304] FIG. 25 illustrates a case where an electronic device including a display module (2310; see FIG. 23) is applied to a wearable electronic device. The wearable electronic device may be smart glasses (2300_2a), a head-mounted display (2300_2b), a smart watch (2300_2c), etc.

[0305] Smart glasses (2300_2a) and a head-mounted display (2300_2b) may include a display module (2310; see FIG. 23) that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing the user with a virtual reality (VR) or augmented reality (AR) screen.

[0306] The smart watch (2300_2c) may include a bio-sensor as an input module (2350; see FIG. 23). The smart watch (2300_2c) may provide bio-information recognized through the bio-sensor to the user through a display module (2310; see FIG. 23).

[0307] FIG. 26 illustrates a case where an electronic device including a display module (2310; see FIG. 23) is applied to a vehicle. For example, the electronic device (2300_3) may be applied to the instrument panel, center fascia, etc. of the vehicle, or may be applied to a Center Information Display (CID) placed on the dashboard of the vehicle or a room mirror display that replaces a side mirror.

[0308] Although not illustrated, electronic devices to which the display device according to the embodiments is applied may include not only devices primarily focused on screen display, such as billboards, electronic display boards, and game consoles, but also various home appliances that display information through display modules, such as refrigerators, washing machines, dryers, air conditioners, and robot vacuum cleaners. Additionally, if the display module has a function of transmitting light, it may be applied to electronic devices such as smart windows or transparent display devices that display both a background and a display image. The types of electronic devices according to the embodiments are not limited to those exemplified above, and various other electronic devices not exemplified may also be applied.

[0309] The drawings and detailed description of the invention referenced so far are merely exemplary of the invention and are used only for the purpose of explaining the invention, not to limit the meaning or the scope of the invention as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0310] 100: Display device 110: Display panel 120: Data driving circuit 130: Scanning driving circuit 140: Timing Controller 150: Power supply circuit HST: Host DS, 2300: Electronic device ST, 500, 600, 700, 1700: Stage circuit 501, 502, 503, 504, 505, 506, 507, 1701, 1702, 1703, 1704, 1705, 1706: terminal TR1, ..., TR9: Transistors C1, C2, C3: Capacitors 800, 900, 1300, 1800: Driving method 2310: Display module 2320: Processor 2330: Memory 2340: Power module 2350: Input Module 2360: Output Module 2370: Communication Module

Claims

Claim 1 A stage circuit comprising: a first input terminal into which a clock signal is input; a second input terminal into which a driving signal is input; an output terminal that outputs a carry signal; an input unit configured to transmit the driving signal to a first node in response to the clock signal; a signal processing unit that controls the voltages of a Q node and a QB node in response to the driving signal input to the first node; and a carry output unit comprising a boosting capacitor connected to the Q node and the output terminal, respectively, and a buffer capacitor configured to maintain the voltage of the output terminal. Claim 2 In claim 1, the input section comprises a gate electrode electrically connected to the first input terminal and a first transistor configured to switch the electrical connection between the second input terminal and the first node, forming a stage circuit. Claim 3 A stage circuit according to claim 1, further comprising: a third input terminal to which a high-level voltage is input; and a fourth input terminal to which a low-level voltage is input, wherein the signal processing unit comprises: a second transistor configured to switch the electrical connection between the third input terminal and the QB, wherein the second transistor comprises a gate electrode electrically connected to the first node; a third transistor configured to switch the electrical connection between the first node and the Q node; a fourth transistor configured to switch the electrical connection between the fourth input terminal and the QB node, wherein the fourth transistor comprises a gate electrode electrically connected to the Q node; and a stabilizing capacitor comprising a first electrode electrically connected to the QB node and a second electrode electrically connected to the third input terminal. Claim 4 In paragraph 3, the buffer capacitor is a stage circuit directly connected to the fourth input terminal. Claim 5 In paragraph 3, the stage circuit wherein the second transistor and the third transistor are transistors comprising a P-type semiconductor, and the fourth transistor is a transistor comprising an N-type semiconductor. Claim 6 In paragraph 3, the third transistor is a stage circuit comprising a gate electrode electrically connected to the fourth input terminal. Claim 7 In paragraph 3, the low-level voltage input to the fourth input terminal is a first low-level voltage, and the stage circuit further includes a seventh input terminal to which a second low-level voltage is input, and the third transistor is a stage circuit including a gate electrode electrically connected to the seventh input terminal. Claim 8 In claim 7, the second low-level voltage is a stage circuit lower than the first low-level voltage. Claim 9 In claim 7, the buffer capacitor is a stage circuit directly connected to the 7th input terminal. Claim 10 In paragraph 3, at least one of the second transistor, the third transistor, and the fourth transistor is a stage circuit having a four-terminal structure including a back gate electrode. Claim 11 In claim 1, the output terminal is a second output terminal, and the stage circuit further comprises: a third input terminal into which a high-level voltage is input; a fourth input terminal into which a low-level voltage is input; a first output terminal for outputting a scan signal; and a scan output unit for outputting the scan signal according to the voltages of the Q node and the QB node, wherein the scan output unit comprises: a fifth transistor configured to switch the electrical connection between the third input terminal and the first output terminal in response to the voltage of the QB node; and a sixth transistor configured to switch the electrical connection between the fourth input terminal and the first output terminal in response to the voltage of the Q node. Claim 12 In claim 11, the fifth transistor and the sixth transistor are stage circuits comprising a P-type semiconductor. Claim 13 A stage circuit according to claim 1, further comprising: a third input terminal to which a high-level voltage is input; and a fourth input terminal to which a low-level voltage is input, wherein the carry output unit comprises a gate electrode electrically connected to the QB node and a seventh transistor configured to switch the electrical connection between the third input terminal and the output terminal; and an eighth transistor configured to switch the electrical connection between the fourth input terminal and the output terminal and a gate electrode electrically connected to the Q node. Claim 14 In paragraph 13, each of the seventh transistor and the eighth transistor comprises a stage circuit including a P-type semiconductor. Claim 15 A stage circuit according to claim 1, further comprising: a fifth input terminal to which a reset signal is input; a sixth input terminal to which a low-level voltage is input; and a reset unit, wherein the reset unit comprises a gate electrode electrically connected to the fifth input terminal and a ninth transistor configured to switch the electrical connection between the sixth input terminal and the QB node. Claim 16 A display device comprising: a display panel having a plurality of pixels arranged thereon and scanning lines electrically connected to the plurality of pixels arranged thereon; a scanning driving circuit comprising a plurality of stage circuits configured to supply a scanning signal to the plurality of scanning lines, wherein at least one of the plurality of stage circuits comprises: a first input terminal into which a clock signal is input; a second input terminal into which a driving signal is input; a first output terminal for outputting the scanning signal; a second output terminal for outputting a carry signal; an input unit configured to transmit the driving signal to a first node in response to the clock signal; a signal processing unit for controlling the voltage of a Q node and a QB node in response to the driving signal input to the first node; a carry output unit comprising a boosting capacitor connected to the Q node and the output terminal, respectively, and a buffer capacitor configured to maintain the voltage of the second output terminal; and a scanning output unit for outputting the scanning signal according to the voltage of the Q node and the QB node. Claim 17 A display device according to claim 16, further comprising: a third input terminal to which a high-level voltage is input; and a fourth input terminal to which a low-level voltage is input, wherein the signal processing unit comprises: a second transistor configured to switch the electrical connection between the third input terminal and the QB, the second transistor comprising a gate electrode electrically connected to the first node; a third transistor electrically connecting the first node and the Q node; a fourth transistor comprising a gate electrode electrically connected to the Q node and configured to switch the electrical connection between the fourth input terminal and the QB node; and a stabilizing capacitor comprising a first electrode electrically connected to the QB node and a second electrode electrically connected to the third input terminal. Claim 18 A display device according to claim 17, wherein the carry output section further comprises: a seventh transistor configured to switch the electrical connection between the third input terminal and the output terminal, and a gate electrode electrically connected to the Q node; and an eighth transistor configured to switch the electrical connection between the fourth input terminal and the output terminal, and a gate electrode electrically connected to the Q node. Claim 19 An electronic device comprising: a processor for outputting input image data; a display device for displaying an image corresponding to the input image data according to a scan signal generated from a plurality of stage circuits, wherein at least one of the plurality of stage circuits comprises: a first input terminal into which a clock signal is input; a second input terminal into which a driving signal is input; a first output terminal for outputting the scan signal; a second output terminal for outputting a carry signal; an input unit configured to transmit the driving signal to a first node in response to the clock signal; a signal processing unit for controlling the voltages of a Q node and a QB node in response to the driving signal input to the first node; a carry output unit including a boosting capacitor connected to the Q node and the output terminal, respectively, and a buffer capacitor configured to maintain the voltage of the second output terminal; and a scan output unit for outputting the scan signal according to the voltages of the Q node and the QB node. Claim 20 In claim 19, the processor further outputs a control signal, and the display device is an electronic device configured to generate a scan control signal configured to control the driving timing of the stage circuits in response to the control signal.

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