Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

Abstract

A semiconductor gate structure includes a shielding electrode and a switching electrode. Portions of a shield electrode are located over the drain region and the well region. The first dielectric layer is located between the shielding electrode and the drain and well regions. Portions of switch electrodes are located over the well region and the source region. A second dielectric layer is located between the switch electrode and the well and source regions. A third dielectric layer is located between the shield electrode and the switch electrode.

Description

[0001] Related patent application reference [0002] This patent application claims the benefit of priority to US Provisional Patent Application Serial No. 60 / 405,369, filed August 23,2002. technical field [0003] This invention relates to semiconductors, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs). Background technique [0004] MOSFETs are widely used in the field of switching, for example, switching power supplies hardly use other types of transistors. MOSFETs are suitable for this switching application because they have a relatively high switching speed and require low power. However, dynamic losses in MOSFETs account for a large percentage of the total losses in a DC-DC converter. The dynamic loss is directly proportional to the rise and fall time of the device, and the rise and fall time of the device is proportional to the gate-drain capacitance of the device, that is, the Miller capacitance (C GD or Q GD ) proportional to...

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Problems solved by technology

However, the ability to further reduce the channel width is limited by the ability to etch the narrow channel, and there is a corresponding need to be able to fill this narrow channel with gate electrode material

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