Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FAIRCHILD SEMICON CORP
- Publication Date
- 2006-07-26
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
[0001] Related patent application reference
[0002] This patent application claims the benefit of priority to US Provisional Patent Application Serial No. 60 / 405,369, filed August 23,2002. technical field
[0003] This invention relates to semiconductors, and more particularly to metal oxide semiconductor field effect transistors (MOSFETs). Background technique
[0004] MOSFETs are widely used in the field of switching, for example, switching power supplies hardly use other types of transistors. MOSFETs are suitable for this switching application because they have a relatively high switching speed and require low power. However, dynamic losses in MOSFETs account for a large percentage of the total losses in a DC-DC converter. The dynamic loss is directly proportional to the rise and fall time of the device, and the rise and fall time of the device is proportional to the gate-drain capacitance of the device, that is, the Miller capacitance (C GD or Q GD ) proportional to...