35results about How to "Effective capacitance" patented technology

A capacitive position sensor comprising a preferably annular sensing path, the sensing path having one or more virtual buttons designated along its length. The sensing path has a plurality of terminals connected to it to subdivide it into a plurality of sections, each terminal providing a sensing channel for a signal indicative of capacitance. The sensing channels provide the signals to a processor, preferably a microcontroller, that is operable to distinguish between a user making a touch to actuate one of the virtual buttons, and a touch to perform a scrolling function. To be determined as a scroll, it is required that there is a succession of detects which span over at least a threshold distance, for example an angular or linear distance. To be determined as a touch, it is required that there is a succession of detects that all lie within one of the pre-assigned virtual button positions.

A stud or joist sensor device and associated sensing method using a ratio of capacitance measurements from a plurality of capacitive sensing elements. The device locates a feature of an object or discontinuity behind a surface or wall, such as an edge and/or a center of a stud behind the surface, a joist under a floorboard, a gap behind sheetrock, a metal conductor behind a surface or the like. The device may be moved over a surface, thereby detecting changes in capacitance. The change in capacitance is due to the effective dielectric constant caused by the passage over an object such as a stud. When two capacitive sensing elements provide equivalent capacitance measures, the device is over a centerline of the stud. When a ratio of the capacitance measurements equals a transition ratio, the device is over an edge of the stud.

Dielectric compositions that include compound of the formula [(M′)_1−x(A′)_x][(M″)_1−y−z,(B″)_y(C″)_z]O_3−δ(V_O)_δ and protonated dielectric compositions that include a protonated dielectric compound within the formula [(M′)_1−x(A′)_x](M″)_1−y−z(B″)_y(C″)_z]O_3−δ+h(V_o)_δ(H*)_2h are disclosed. Composite materials that employ one or more of these dielectric compounds together with an electrolyte also are disclosed. Composite material that employs one or more of these dielectric compounds together with an electrochemally active material also are disclosed.

The present invention provides a chemiresistor-based sensor for measuring the presence or amount of analyte in an electrolyte solution; said chemiresistor comprising (i) a chemiresistor film wherein the impedance of said nanoparticle film changes in the presence of an analyte; and (ii) two electrically conducting electrodes in electrical contact with said nanoparticle film; wherein said electrically conducting electrodes are adapted to be connected to a device for measuring the impedance of said chemiresistor film under a voltage signal and wherein the impedance of the double layer capacitor formed by the two electrically conducting electrodes in the presence of the electrolyte solution, is larger than the impedance of the chemiresistor film either before or after exposure of the chemiresistor film to the analyte. A method of using said chemiresistor-based sensor to measure the presence or amount of analyte is also provided. Further provided is a method of determining the partition coefficient of an analyte using said chemiresistor-based sensor.

A touch panel includes a first sensing electrode layer formed on a first surface of a transparent substrate, the first sensing electrode layer having plural first electrodes. Plural first dummy electrodes are disposed among the first electrodes of the first sensing electrode layer respectively, and are electrically insulated from the first electrodes. A second sensing electrode layer is formed on a second surface being opposite to the first surface. The second sensing electrode layer includes plural second electrodes, which are disposed complementally in relation to the first electrodes.

A capacitor, and methods of its manufacture, having improved capacitance efficiency which results from increasing the effective area of an electrode surface are disclosed. An improved “three-dimensional” capacitor may be constructed with electrode layers having three-dimensional aspects at the point of interface with a dielectric such that portions of the electrode extend into the dielectric layer. Advantageously, embodiments of a three-dimensional capacitor drastically reduce the space footprint that is required in a circuit to accommodate the capacitor, when compared to current capacitor designs. Increased capacitance density may be realized without using high k (high constant) dielectric materials, additional “electrode-dielectric-electrode” arrangements in an ever increasing stack, or serially stringing together multiple capacitors.

A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.

A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.

A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P⁺/N⁻ or N⁺/P⁻ junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P⁺/N⁻ or N⁺/P⁻ junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.

A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.

The present disclosure is applied to touch technology, and provides an integrating circuit. The integrating circuit comprises an impedance unit, an amplifier, an integration capacitor, a discharge capacitor, a first switch and a second switch. The amplifier comprises a first input terminal, a second input terminal and an output terminal configured to output an output signal; the integration capacitor is coupled between the first input terminal and the output terminal; the first switch is coupled between the first input terminal of the amplifier and the second terminal of the discharge capacitor; and the second switch is coupled between the first terminal and the second terminal of the discharge capacitor.

A method for reducing a delay, between a transition of a transmission of a metal detector and a process of a receive signal received by a receive coil of the metal detector, due to a critically damped time constant of the receive coil, including: introducing a negative capacitance into the receive coil to reduce the critically damped time constant.

The invention relates to an image sensor with matrix readout including a matrix of elementary photodetectors (P) connected through at least a bus (Bpel) to a remote integrator (I) which converts the signal of each elementary photodetector into a voltage, characterized in that it includes, between the end of the bus and the input of the integrator, an impedance matching device (D) with low output capacitance, delivering at its output, during the time for converting a photodetector signal, a variation of charge which corresponds to an affine function of the charge present at the input of said matching device, wherein this charge variation is determined by: <math-cwu id="MATH-US-00001"> <number>1</number> ${\int }_{t=0}^{t=\mathrm{Tconv}}\mathrm{Iinj}\left(t\right)·dt={\int }_{t=0}^{t=\mathrm{Tconv}}I\mathrm{int}\left(t\right)·dt$ <mathematica-file id="MATHEMATICA-00001" file="US20010048065A1-20011206-M00001.NB"/> <image id="EMI-M00001" wi="216.027" he="19.93005" file="US20010048065A1-20011206-M00001.TIF" imf="TIFF" ti="MF"/> </math-cwu> where Iinj is the instantaneous current of the bus, injected at the input of the impedance matching device, Iint is the instantaneous current at the input of the integrator and Tconv is the conversion time.

A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.