32results about How to "Low effective capacitance" patented technology

A method of forming a device includes providing a transistor having a gate structure and a source/drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source/drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source/drain structure. A metal plug is then formed over the portion of the exposed source/drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.

Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.

The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element and at least one second capacitive element which is connected in series with the first capacitive element. A node is provided between the first capacitive element and at least one second capacitive element. The oscillator circuit contains a damping reduction amplifier which is arranged in parallel with the frequency-determining resonant circuit. In addition, the oscillator circuit has a first tuneable capacitive element, which is connected in parallel with the first capacitive element of the resonant circuit and has a connection connected to the node.

The spark clearance has as much possible partial spark clearances connected in series, in particular, these partial spark clearances are wired by capacitor (6) except the first spark clearance reacting in the case of overvoltage phenomenon, and, in particular, the second spark clearance and each spark clearance other than it are connected with common reference electric potential (4), particularly, ground potential through the capacity (6). To markedly improve reaction characteristic of a spark clearance, a bypass (7) composed of an auxiliary spark clearance (8) having a smaller reaction voltage than a reaction voltage of a single spark clearance or these partial spark clearances and at least one varistor (9) is connected in parallel with a multiple spark clearance composed of the single spark clearance or a plurality of partial spark clearances connected in series.

The invention provides a major loop electric power cable for a medium-voltage frequency converter. The cable comprises three power conductors, three control conductors and a central gap filler, wherein the cross section of the central gap filler is round, a cabled core is formed by stranding of the three power conductors and the three control conductors around the central gap filler, the control conductors are arranged between any two adjacent power conductors, the cabled core is sequentially coated with a third metal shielding layer, an electrostatic shielding layer, a water-blocking tape covering layer, a tin-plated steel wire winding armor layer and a polyolefin outer sheath, and water-blocking ropes with triangular cross sections are placed in gaps between the power conductors, the control conductors and the third metal shielding layer. According to the major loop electric power cable for the medium-voltage frequency converter, effective capacitance is low, transfer impedance is low, good electromagnetic compatibility is achievable, the tensile strength and water resistance of the cable are improved, and the service life of the cable is prolonged.

A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate, a gate structure, a side wall located on the side wall of the gate structure, a source-drain doped region, a bottom dielectric layer and a source-drain contact layer; removing the side wall to form a gap; forming a protective layer covering the bottom and the side wall of the gap in a shape-preserving manner; and forming a top dielectric layer on the bottom dielectric layer, wherein the top dielectric layer seals the gap to form an air gap. According to the embodiment of the invention, after the substrate is provided, the side walls are removed to form the gap, the bottom and the side walls of the gap are covered with the protective layer in a shape-preserving manner, and then the top dielectric layer for sealing the gap is formed, so that the air gap and the protective layer are correspondingly of an integrated structure, and the protection effect of the protective layer on the bottom and the side walls of the gap is improved; the damage probability of the film layer structures (such as the gate structure and the substrate) at the bottom and the side wall of the gap is reduced, the integrity of the film layer structures at the bottom and the side wall of the gap is correspondingly improved, and then the reliability and the production yield of the semiconductor structure are improved.