33results about How to "Low effective capacitance" patented technology

A portable ambient air quality monitor having an enclosure to enclose and protect the monitor from an ambient environment and an airflow intake for controllably allowing ambient air to enter the monitor. A photodiode is disposed at a location downstream from a fan. The airflow from the fan is laminarized by a mesh or baffle to allow a thin stream of air to flow over the photodiode. A sensing region is defined by an intersection of an airflow sampling path and an optical path. The sensing region is also disposed above the photodiode. The airflow sampling path is configured to receive laminar airflow from the airflow intake and for directing the laminar airflow into the sensing region. A light beam is generated from a laser to reflect the light beam for reducing the required area of the sensing region to detect and measure the particles floating in the ambient air.

A capacitive sensing circuit including a microchip and a sense plate, wherein the microchip comprises a hardware Q RF noise detector module that provides a logical indication of when noise impacts on the integrated circuit.

A method of forming a device includes providing a transistor having a gate structure and a source / drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source / drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source / drain structure. A metal plug is then formed over the portion of the exposed source / drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

The invention discloses a transformer without Y capacitor, comprising a magnetic core, a primary main winding, a secondary winding and an auxiliary winding, wherein the primary main winding, the secondary winding and the auxiliary winding are successively winded on the magnetic core. The transformer further comprises a primary shielded winding connected with the primary main winding and a secondary shielded winding connected with the secondary winding, wherein the primary shielded winding and the secondary shielded winding have the same number of loops and the same phase. The invention solvestwo main problems of electromagnetic radiation and electric leakage in a switch power supply at the same time, realizes that the switch power supply can pass an electromagnetic radiation test withoutY capacitor, so the transformer is suitable for products fairly sensitive to leakage current, such as mobile phone chargers.

A portable ambient air quality monitor having an enclosure to enclose and protect the monitor from an ambient environment and an airflow intake for controllably allowing ambient air to enter the monitor. A photodiode is disposed at a location downstream from a fan. The airflow from the fan is laminarized by a mesh or baffle to allow a thin stream of air to flow over the photodiode. A sensing region is defined by an intersection of an airflow sampling path and an optical path. The sensing region is also disposed above the photodiode. The airflow sampling path is configured to receive laminar airflow from the airflow intake and for directing the laminar airflow into the sensing region. A light beam is generated from a laser to reflect the light beam for reducing the required area of the sensing region to detect and measure the particles floating in the ambient air.

A method of constructing a differential inductor having a high self-resonance frequency is provided. In general, a ground point is identified. A first coil having a first and second loop is created such that the first loop is electrically further away from the ground point than the second loop. A second coil having a third and fourth loop are created such that the third loop is electrically further away from the ground point than the second loop. The first coil and the second coil are positioned such that the first loop is positioned as a near neighbor to said fourth loop and said second loop is positioned as a near neighbor to said third loop.

Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.

A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.

Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.

Systems and methods for controlling the effective dielectric constant of materials used in a semiconductor device are shown and described. In one embodiment, a method comprises providing a semiconductor substrate with a plurality of pillars formed thereon, depositing a first layer of dielectric material over a plurality of pillars, removing a portion of the first layer deposited over the plurality of pillars, and depositing a second layer of dielectric material over the plurality of pillars, where the second layer leaves a plurality of voids between the plurality of pillars.

A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature / low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

A method of forming a device includes providing a transistor having a gate structure and a source / drain structure adjacent to the gate structure. A cavity is formed along a sidewall surface of a contact opening over the source / drain structure. After forming the cavity, a sacrificial layer is deposited over a bottom surface and along the sidewall surface of the contact opening including within the cavity. A first portion of the sacrificial layer along the bottom surface of the contact opening is removed to expose a portion of the source / drain structure. A metal plug is then formed over the portion of the exposed source / drain structure. A remaining portion of the sacrificial layer is removed to form an air gap disposed between the metal plug and the gate structure. Thereafter, a seal layer is deposited over the air gap to form an air gap spacer.

The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element and at least one second capacitive element which is connected in series with the first capacitive element. A node is provided between the first capacitive element and at least one second capacitive element. The oscillator circuit contains a damping reduction amplifier which is arranged in parallel with the frequency-determining resonant circuit. In addition, the oscillator circuit has a first tuneable capacitive element, which is connected in parallel with the first capacitive element of the resonant circuit and has a connection connected to the node.

The invention is directed to an oscillator circuit in which a frequency-determining resonant circuit includes an inductive element, a first capacitive element and at least one second capacitive element which is connected in series with the first capacitive element. A node is provided between the first capacitive element and at least one second capacitive element. The oscillator circuit contains a damping reduction amplifier which is arranged in parallel with the frequency-determining resonant circuit. In addition, the oscillator circuit has a first tuneable capacitive element, which is connected in parallel with the first capacitive element of the resonant circuit and has a connection connected to the node.

A carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. In some embodiments, the dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen. The carbon-rich silicon carbide-like dielectric film can be used as a dielectric cap layer in an interconnect structure. The inventive dielectric film is highly robust to UV curing and remains compressively stressed after UV curing. Moreover, the inventive dielectric film has good oxidation resistance and prevents metal diffusion into an interconnect dielectric layer. The present invention also provides an interconnect structure including the inventive dielectric film as a dielectric cap. A method of fabricating the inventive dielectric film is also provided.

A capacitive sensing circuit including a microchip and a sense plate, wherein the microchip comprises a hardware Q RF noise detector module that provides a logical indication of when noise impacts on the integrated circuit.

The spark clearance has as much possible partial spark clearances connected in series, in particular, these partial spark clearances are wired by capacitor (6) except the first spark clearance reacting in the case of overvoltage phenomenon, and, in particular, the second spark clearance and each spark clearance other than it are connected with common reference electric potential (4), particularly, ground potential through the capacity (6). To markedly improve reaction characteristic of a spark clearance, a bypass (7) composed of an auxiliary spark clearance (8) having a smaller reaction voltage than a reaction voltage of a single spark clearance or these partial spark clearances and at least one varistor (9) is connected in parallel with a multiple spark clearance composed of the single spark clearance or a plurality of partial spark clearances connected in series.

The invention provides a major loop electric power cable for a medium-voltage frequency converter. The cable comprises three power conductors, three control conductors and a central gap filler, wherein the cross section of the central gap filler is round, a cabled core is formed by stranding of the three power conductors and the three control conductors around the central gap filler, the control conductors are arranged between any two adjacent power conductors, the cabled core is sequentially coated with a third metal shielding layer, an electrostatic shielding layer, a water-blocking tape covering layer, a tin-plated steel wire winding armor layer and a polyolefin outer sheath, and water-blocking ropes with triangular cross sections are placed in gaps between the power conductors, the control conductors and the third metal shielding layer. According to the major loop electric power cable for the medium-voltage frequency converter, effective capacitance is low, transfer impedance is low, good electromagnetic compatibility is achievable, the tensile strength and water resistance of the cable are improved, and the service life of the cable is prolonged.

A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region and a lower doped region which have different types of doping to form a PN junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PN junction is in series with the intrinsic gate-to-drain capacitance. Accordingly, the effective capacitance between the gate and the drain may be reduced.

A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature / low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source / drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

The invention discloses a four-corner snakelike bridge broadband electromagnetic band gap structure, and belongs to the technical field of circuit microwaves. According to the structure, complementary split-ring resonator shape etching is carried out at the center, and the snake-shaped bridge structures are arranged between the adjacent units, so that the inductance between the electromagnetic band gap units is increased, low-frequency-band SSN is effectively suppressed, the bandwidth is relatively wide, and SSN of a stop band can be effectively suppressed. The four sides of the EBG structure are etched into rectangles, and adjacent elements are connected to form a bridge. Compared with a traditional L-bridge structure, the S-shaped structure is designed, so that the surface current path can be increased, and the equivalent inductance and the equivalent capacitance are increased. The gap between the resonant rings generates a gap current and generates a resonant circuit, so that the cut-off frequency can be effectively reduced and the width of a stop band can be improved. The ultra-wide band gap structure takes the suppression depth of-30dB as a standard, can reach an ultra-wide band gap of 23.8 GHz, is obviously superior to a conventional electromagnetic band gap structure, and can better suppress the noise of a synchronous switch.

The invention provides a major loop electric power cable for a medium-voltage frequency converter. The cable comprises three power conductors, three control conductors and a central gap filler, wherein the cross section of the central gap filler is round, a cabled core is formed by stranding of the three power conductors and the three control conductors around the central gap filler, the control conductors are arranged between any two adjacent power conductors, the cabled core is sequentially coated with a third metal shielding layer, an electrostatic shielding layer, a water-blocking tape covering layer, a tin-plated steel wire winding armor layer and a polyolefin outer sheath, and water-blocking ropes with triangular cross sections are placed in gaps between the power conductors, the control conductors and the third metal shielding layer. According to the major loop electric power cable for the medium-voltage frequency converter, effective capacitance is low, transfer impedance is low, good electromagnetic compatibility is achievable, the tensile strength and water resistance of the cable are improved, and the service life of the cable is prolonged.

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate, a gate structure, a side wall located on the side wall of the gate structure, a source-drain doped region, a bottom dielectric layer and a source-drain contact layer; removing the side wall to form a gap; forming a protective layer covering the bottom and the side wall of the gap in a shape-preserving manner; and forming a top dielectric layer on the bottom dielectric layer, wherein the top dielectric layer seals the gap to form an air gap. According to the embodiment of the invention, after the substrate is provided, the side walls are removed to form the gap, the bottom and the side walls of the gap are covered with the protective layer in a shape-preserving manner, and then the top dielectric layer for sealing the gap is formed, so that the air gap and the protective layer are correspondingly of an integrated structure, and the protection effect of the protective layer on the bottom and the side walls of the gap is improved; the damage probability of the film layer structures (such as the gate structure and the substrate) at the bottom and the side wall of the gap is reduced, the integrity of the film layer structures at the bottom and the side wall of the gap is correspondingly improved, and then the reliability and the production yield of the semiconductor structure are improved.

A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P+ / N− or N+ / P− junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P+ / N− or N+ / P− junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.

The invention provides a chip type high polymer electrostatic discharge protecting element. Inner electrodes are one of two inner electrodes opposite to each other in a length direction and two inner electrodes staggered with each other in the length direction; and a core material is one of a core material filled in a gap between the two inner electrodes opposite to each other in the length direction, a core material filled in a gap between the two inner electrodes staggered with each other in the length direction, and a core material filled in a through hole in the gap between the two inner electrodes opposite to each other in the length direction. The manufacturing method sequentially comprises the following steps: (1) the preparation of slurry of the core material; (2) the preparation of a lower substrate; (3) the preparation of the inner electrodes; (4) the preparation of the core material; (5) the preparation of an upper substrate; (6) cutting of a chip; (7) the preparation of terminal electrodes; and (8) electroplating. A chip type ESD (Electrostatic Discharge) protecting device which has small size and very small effective capacitance can be manufactured; the requirements of high-speed signal transmission equipment on the ESD protection can be sufficiently met; the inner electrodes and the terminal electrodes are easier to connect, and the terminal electrodes are easier to lead out, therefore, the chip type high polymer electrostatic discharge protecting element is easy to manufacture; moreover; and the gap between the inner electrodes can be correspondingly adjusted according to the value of a trigger voltage in the design.