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Joint estimation and real-time correction method for channel error of TIADC system

A channel error and joint estimation technology, which is applied to baseband system components, transmitter/receiver shaping networks, etc., can solve the problems of high time overhead and lack of real-time performance of offline methods

Inactive Publication Date: 2011-05-25
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

When the scale of the system channel is expanded, the time overhead of the offline method is relatively large, and it does not have real-time performance

Method used

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  • Joint estimation and real-time correction method for channel error of TIADC system
  • Joint estimation and real-time correction method for channel error of TIADC system
  • Joint estimation and real-time correction method for channel error of TIADC system

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Embodiment Construction

[0048] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0049] Such as figure 1 Shown is the structural block diagram of the TIADC sampling system, also known as the multi-channel parallel time-alternating sampling system. Assuming that the sampled input analog signal is x(t), the sampling interval of the entire sampling system is T s =1 / f s , if the total number of channels is M, then the single-channel sampling interval T=MT s , this is a parallel sampling platform with M channels, so there are M sets of sampling circuits that work independently, and the sampling data of M channels x k (n) After being spliced ​​together by ...

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Abstract

The invention discloses a joint estimation and real-time correction method for channel error of a time-interleaved ADC (TIADC) system. The method for implementing joint estimation comprises the steps of: sampling a single-tone signal with input frequency of f0 to obtain a sampling sequence xk(n) of various channels of the system, wherein k=0, 1, L M-1; performing fast Fourier transform (FFT) on sampling data x(n) which is reduced into a single-tone signal after the split joint; and in an FFT result, selecting a value FAk at the position where the frequency is 1fs / M+ / -f0,1=0, 1L M-1 and selecting a value FBk at the position where the frequency is 1fs / M,1=0, 1L M-1 to perform inverse fast Fourier transform (IFFT) to obtain M complex numbers, namely IAk and IBk, and finally, obtaining the joint estimation on time error delta tk, gain error gk, and offset error ok, k=0, 1, L M-1 through phase angle extraction and a modulus operation algorithm module. The method for implementing real-time correction comprises the step of: utilizing a comprehensive correction mechanism formed by a subtractor, a divider and a fractional delay filter to correct the offset error, the gain error and the time error existing in the sampling data of the channels respectively. By the method, joint estimation is performed on the three errors, SFDR of the sampling sequence is improved through the real-time correction, and a filter coefficient is not required to be updated or a correction module is not required to be redesigned even if channel errors are changed, so the aim of the real-time correction is fulfilled.

Description

technical field [0001] The invention belongs to the technical field of high-speed and high-precision sampling, and more specifically relates to a method for joint estimation and real-time correction of TIADC system channel errors. Background technique [0002] With the development of large-scale integrated circuits, digital signal processing technology and microcomputers, many digital signal processing equipment, such as radar systems, modern communications, remote sensing and telemetry, etc., have put forward more and more requirements for the speed and accuracy of the analog-to-digital conversion system (ADC). Come higher demands. However, limited by the manufacturing process of the device itself, it is difficult for a single-chip ADC to meet the high-precision requirements at the same time as high speed. One of the sampling rate methods. [0003] If the parallel time-alternating ADC sampling system is ideal, the performance of each ADC is exactly the same, and the sampl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L25/02H04L25/03
Inventor 王志刚王猛王俊丽郑冬
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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