39results about How to "Reduce output load" patented technology

Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1 / n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.

A power converter provides power to a phased-array radar antenna system. The converter adjusts its internal zero-voltage switching current so that it efficiently provides a clean power signal over a wide range of potential loads. More specifically, the zero-voltage switching current is increased in response to a decrease in load. The zero-voltage switching current in the converter can be maintained based on use of the same control signals that are otherwise used to regulate (via switching) the voltage output of the converter.

It is an object of the invention to reduce loads of outputs from pixels and suppress a decrease in gain, a reduction in a speed, and the like in a solid-state image pickup device having a circuit for adding (averaging) a plurality of pixel signals. The device has a plurality of pixels which are one-dimensionally or two-dimensionally arranged and output photoelectrically converted signals and a plurality of output lines to which the output signal(s) from one pixel or the pixels arranged on one column is / are outputted. A signal adder circuit for arbitrarily adding the output signals from the plurality of output lines and outputting an addition signal and a signal output circuit for outputting each of the output signals, as individual signals, from the plurality of output lines without adding them are independently provided.

A receiving circuit comprises a transimpedance amplifier 3 including an inversion amplifier 2 for amplifying an input current IN, and a feedback resistance R1 connected between an input and an output of the inversion amplifier 2, a comparison circuit 4 for comparing an output OUT of the transimpedance amplifier 3 with a certain desired reference value, and outputting a result of the comparison, and a control circuit for holding the comparison result, and generating an AGC signal 20 for adjusting a gain of the transimpedance amplifier 3. The transimpedance amplifier 20 has a function capable of gain adjustment in accordance with the input AGC signal 20. The control circuit 5 performs gain adjustment until the output OUT of the transimpedance amplifier 3 exceeds the reference value so that an appropriate gain is obtained. Therefore, even when an input has a wide dynamic range, it is possible to prevent signal satuation and a distortion in output waveform in the transimpedance amplifier, so that appropriate reception can be invariably performed and a signal having a stable duty can be output.

A data transmitting method for inputting a data signal to an electronic device. The data signal includes first and second sets of data, and the electronic device includes first to fourth receiving units and corresponding first to fourth registers. The transmitting method includes the following steps. First, the first and second receiving units are disabled. Then, the first set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers during a first clock cycle of a clock signal. Thereafter, the second set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers while the first set of data stored in the third and fourth registers is inputted to the first and second registers during a second clock cycle of the clock signal.

According to an aspect of the present disclosure, a gate driver includes a plurality of stages which is dependently connected to each other and each of the plurality of pixels includes: a first output unit which outputs a sensing signal by voltages of a Q node and a QB node; a second output unit which outputs a reference signal by the voltages of the Q node and the QB node; a third output unit which outputs a scan signal by the voltages of the Q node and the QB node; a first controller which controls the Q node; and a second controller which controls the QB node, and at least two of the first to third output units share at least one clock signal among a plurality of clock signals, thereby reducing an area of the gate driver.

The invention provides an electro-hydraulic proportional solenoid valve. The valve comprises a valve core, an oil outlet valve sleeve, a guide sleeve, a magnetism isolating ring, a pole shoe and a coil, wherein the magnetism isolating ring is of a non-magnetic material; the two ends of the magnetism isolating ring are connected with the guide sleeve and the pole shoe respectively to form a sleeve; the coil is arranged on the outer side of the sleeve; the oil outlet valve sleeve is provided with at least one oil outlet hole; one end of the oil outlet valve sleeve is in interference fit with the guide sleeve; the outer circumferential surface of the end part at one end of the valve core is provided with at least one oil inlet wedged groove, and the end face is provided with a straight groove which is communicated with the oil inlet wedged groove; the valve core is positioned in the sleeve; the position of the oil inlet wedged groove corresponds to the position of the oil outlet hole and is not overlapped with the oil outlet hole; a pre-tightening screw is arranged in the pole shoe; a return spring is arranged between the pre-tightening screw and the valve core. The assist characteristic of an automobile steering system can be continuously changed with vehicle speed, so the assist effect is better; the valve has the advantages of compact structure, easiness in control and low cost.

The invention discloses a method for reducing and controlling losses of nitrogen and phosphorus of rice, belonging to a method of zero tillage and standard open tillage of the rice and comprising the following steps of: digging a surrounding ditch around the rice; digging a waist ditch and a side ditch for dividing the rice into several side surfaces; flattening the side surfaces; fertilizing enough basic fertilizers; coating films for tightly attaching ground films to clay on the side surfaces; pressing both sides by using the clay; transplanting the rice; keeping water in the ditches rather than in the film surfaces; drying the water in the rice within 15 days before the rice is ripe; and leaving low rice stubble in rice harvest. In the method, irrigation with water saving is realized, the purpose for reducing and controlling the losses of nitrogen and phosphorus of the rice is realized, and a theoretical basis and a realizing mode are supplied for scientifically and reasonably building the environmentally friendly utilization mode of the rice.

A driving circuit drives an electro-optical device in which a gray-scale level of each of a plurality of electro-optical elements provided so as to correspond to a plurality of data lines is controlled on the basis of a voltage of a corresponding data line. The driving circuit includes a pulse output circuit that outputs a plurality of sampling pulses, each of the plurality of sampling pulses becoming an active level sequentially; a plurality of unit circuits each of which is supplied with a sampling pulse from the pulse output circuit; and a signal line that is supplied with a gray-scale signal to sequentially designate a gray-scale level of each of the electro-optical elements. Each of the plurality of unit circuits has a first switching element that samples the gray-scale signal supplied to the signal line in accordance with a sampling pulse output from the pulse output circuit; a second switching element that is inserted between the first switching element and the data line and enters an off state until a predetermined period passes from a time when sampling operation is started by the first switching element; and a storage capacitor that holds a voltage of an output terminal of the second switching element.

The instant disclosure provides a Power Factor Correction (PFC) boost converter including a PFC converter unit and a control unit and a frequency switching modulation method thereof. The control unit outputs a pulse width modulation (PWM) signal to the PFC converter unit for adjusting an electronic power output to a voltage converter. As the output load of the PFC converter unit increases, the control unit increases the frequency of the PWM signal. Conversely, as the output load of the PFC converter unit decreases, the control unit reduces the frequency of the PWM signal. Consequently, the switching loss of the PFC converter unit is reduced.

The invention discloses an oil gas type load reduction pneumatic actuator cylinder and a load reduction method thereof. The actuator cylinder comprises an outer cylinder, an end cover fixed at one end of the outer cylinder, and a fixed piston arranged in the outer cylinder and mounted on a piston rod, wherein the piston rod partially extends outside the end cover; the other end of the outer cylinder is a closed end provided with a pressure gas joint; a floating piston capable of moving in the length direction of the outer cylinder is arranged between the closed end of the outer cylinder and the fixed piston; a pressure gas cavity is formed between the floating piston and the closed end of the outer cylinder; a rodless cavity is formed between the floating piston and the fixed piston; a rod cavity is formed between the fixed piston and the end cover; and the rodless cavity and the rod cavity are communicated to form a differential structure. The actuator cylinder realizes the supply of needed high load in normal working travel, and reduces the load at the travel terminal to reduce the terminal load impact.

The invention relates to a method comprising the following steps:—measuring (S1) a traffic load;—determining (S2), if the traffic load is lower than a first threshold;—decreasing (S3) a maximum used output load of an amplifier of the base station, if the traffic load is lower than the first;—adjusting (S4) an operation point (102; 104; 106; 108; 112; 114; 116; 118; 124) of the amplifier, if the traffic load is lower than the first threshold;—determining (S2), if the traffic load is higher than a second threshold;—increasing (S5) the maximum used output load of the amplifier, if the traffic load is higher than the second threshold; and—adjusting (S4) the operation point of the amplifier, if the traffic load is higher than the second threshold.

The invention discloses a one-bit full adder based on Fin FET mixed logic. The one-bit full adder comprises a summing output circuit and a carry output circuit. The summing output circuit comprises first to fourteenth Fin FETs. The carry output circuit comprises fifteenth to twenty fourth Fin FETs. The one-bit full adder is low in power consumption and power consumption time delay product.

A solid-state image pickup device reduces the load of outputs from pixels and suppresses a decrease in gain, a reduction in a speed, and the like using a circuit for adding (averaging) a plurality of pixel signals. The device has a plurality of pixels which are one-dimensionally or two-dimensionally arranged and output photoelectrically converted signals, and a plurality of output lines to which the output signal(s) from one pixel or the pixels arranged on one column is / are outputted. A signal adder circuit for arbitrarily adding the output signals from the plurality of output lines and outputting an addition signal and a signal output circuit for outputting each of the output signals, as individual signals, from the plurality of output lines without adding them are independently provided.

The invention provides a load adjustable tidal current energy generating device. The device comprises a frame, at least four water turbines, at least four generating die sets and at least four load adjusting die sets, wherein the at least four water turbines are arranged in parallel in the frame; the axis of each water turbine is in the direction vertical to the level; the at least four generating die sets are respectively connected with the at least four turbines; the at least four load adjusting devices are arranged at the frame and positioned at the upstream of the at least four turbines in the water running direction; each load adjusting die set comprises at least one water guide plate, a rotating mechanism and a driver; when the water running speed exceeds the preset running speed, the drivers drive the rotating mechanisms to rotate the water guide plates until the water guide plates are opened; when the water running speed is less than or equal to the preset running speed, the drivers drive the rotating mechanisms to rotate the water guide plates until the water guide plates are closed. With the adoption of the device, the generating die sets can be effectively adjusted to ensure efficient and stable generating.

A receiving circuit comprises a transimpedance amplifier 3 including an inversion amplifier 2 for amplifying an input current IN, and a feedback resistance R1 connected between an input and an output of the inversion amplifier 2, a comparison circuit 4 for comparing an output OUT of the transimpedance amplifier 3 with a certain desired reference value, and outputting a result of the comparison, and a control circuit for holding the comparison result, and generating an AGC signal 20 for adjusting a gain of the transimpedance amplifier 3. The transimpedance amplifier 20 has a function capable of gain adjustment in accordance with the input AGC signal 20. The control circuit 5 performs gain adjustment until the output OUT of the transimpedance amplifier 3 exceeds the reference value so that an appropriate gain is obtained. Therefore, even when an input has a wide dynamic range, it is possible to prevent signal saturation and a distortion in output waveform in the transimpedance amplifier, so that appropriate reception can be invariably performed and a signal having a stable duty can be output.

The invention discloses a device used for fracture exploitation. The device comprises a cylinder block and a piston rod, one end of the piston rod movably penetrates one end face of the cylinder blockand is connected with a piston located inside the cylinder block, and the other end of the piston rod is connected with the power end of a fracturing pump; a feeding opening and a discharging openingare formed in the cylinder block, a suction valve is arranged above the feeding opening, the cylinder block is communicated with a feeding pipe through the feeding opening, a discharging valve is arranged above the discharging opening, the cylinder block is communicated with a discharging pipe through the discharging opening, and a plurality of first grooves are formed in the inner surface of thecylinder block; limiting pads matched with the first grooves and a plurality of filling pads are further included, the height of the limiting pads is larger than the height of the first grooves, andthe height of the filling pads is equal to the height of the first grooves; and second grooves are formed in the side face, in contact with the cylinder block, of the piston, and balls are arranged inthe second grooves. According to the device, the first grooves, the filling pads, the limiting pads, the second grooves and the balls are applied, and the aims of reducing the output load of the power end of the fracturing pump is achieved.

A data transmission method for inputting data signals into an electronic device is disclosed. The data signals comprise a first group of data signals and a second group of data signals, the electronic device comprises a first, a second, a third and a fourth receiving unit and corresponding first, second, third and fourth register. The transmission method includes: non-enabling the first and second receiving unit; in the first sequence period of sequence signals, inputting the first group of data signals passing through the third and the fourth receiving unit into the third and the fourth register of the electronic device; in the second sequence period of the sequence signals, inputting the second group of signals passing through the third and the fourth receiving unit into the third and the fourth register of the electronic device, at the same time inputting the first group of data signals in the third and the fourth register into the first and the second register of the electronic device.

A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected each time a count value is updated. Therefore, an output load is reduced compared to a case where outputs of all the latch circuits are bundled in a wired-OR connection. Further, because there is no need to provide a reset circuit corresponding to each wired-OR wire, it is possible to achieve a reduction in the circuit scale. Furthermore, because a waveform of a signal flowing in the wired-OR wire does not change in a state where internal commands are continuously created in n clock cycles, it is possible to achieve a reduction in the power consumption.

A data transmitting method for inputting a data signal to an electronic device. The data signal includes first and second sets of data, and the electronic device includes first to fourth receiving units and corresponding first to fourth registers. The transmitting method includes the following steps. First, the first and second receiving units are disabled. Then, the first set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers during a first clock cycle of a clock signal. Thereafter, the second set of data is inputted to the electronic device through the third and fourth receiving units and stored in the third and fourth registers while the first set of data stored in the third and fourth registers is inputted to the first and second registers during a second clock cycle of the clock signal.

According to an aspect of the present disclosure, a gate driver includes a plurality of stages which is dependently connected to each other and each of the plurality of pixels includes: a first output unit which outputs a sensing signal by voltages of a Q node and a QB node; a second output unit which outputs a reference signal by the voltages of the Q node and the QB node; a third output unit which outputs a scan signal by the voltages of the Q node and the QB node; a first controller which controls the Q node; and a second controller which controls the QB node, and at least two of the first to third output units share at least one clock signal among a plurality of clock signals, thereby reducing an area of the gate driver.

A transformer feed-back quadrature voltage controlled oscillator (QVCO) is provided, and the QVCO comprises a first half circuit and a second half circuit, and the first half circuit and the second half circuit respectively comprise a first coupling capacitor, a second coupling capacitor, an induction inductor, a PMOS transistor, an NMOS transistor and a frequency modulation circuit. Base electrodes of the PMOS transistor and the NMOS transistor are respectively connected to a first end of the first coupling capacitor and a first end of the second coupling capacitor. The drain electrode of thePMOS transistor is connected with the first end of the induction inductor, the grid electrode of the NMOS transistor is connected to the drain electrode of the PMOS transistor, and the drain electrode of the NMOS transistor is connected to the grid electrode of the PMOS transistor and the second end of the induction inductor. The frequency modulation circuit is connected to the drain electrode ofthe PMOS transistor and the drain electrode of the NMOS transistor.

A driving circuit drives an electro-optical device in which a gray-scale level of each of a plurality of electro-optical elements provided so as to correspond to a plurality of data lines is controlled on the basis of a voltage of a corresponding data line. The driving circuit includes a pulse output circuit that outputs a plurality of sampling pulses, each of the plurality of sampling pulses becoming an active level sequentially; a plurality of unit circuits each of which is supplied with a sampling pulse from the pulse output circuit; and a signal line that is supplied with a gray-scale signal to sequentially designate a gray-scale level of each of the electro-optical elements. Each of the plurality of unit circuits has a first switching element that samples the gray-scale signal supplied to the signal line in accordance with a sampling pulse output from the pulse output circuit; a second switching element that is inserted between the first switching element and the data line and enters an off state until a predetermined period passes from a time when sampling operation is started by the first switching element; and a storage capacitor that holds a voltage of an output terminal of the second switching element.

The invention relates to a novel fluorescent tube arranged on a fluorescent lamp which is originally provided with a universal electronic ballast. The energy-saving fluorescent lamp is characterized by comprising a double-end fluorescent tube 2 and a cylindrical container 3, wherein the double-end fluorescent tube 2 is shorter than the standard fluorescent tube, an inductor 4 which is matched with the electronic ballast 1 in the novel fluorescent tube and used for regulating the work energy consumption of the novel fluorescent tube is arranged in the cylindrical container 3, one end of the inductor 4 is connected with a lamp base arranged at one end of the fluorescent tube 2 through an electric conductor, the other end of the inductor 4 is connected with the induction output end 5 of the universal electronic ballast 1 in the fluorescent lamp, and the other output ends of the electronic ballast 1 are connected with the other lamp bases of the fluorescent tube 2.

The invention relates to an implementation system of a low-voltage reference source. The implementation system solves the existing problem of stripe interference mixed in an image output by an image sensor caused by the facts that low-voltage reference sources of lower than 1.2V are small in variety and high in internal resistance, superimposed interference for burrs is easy on reference voltage when the capacitive load of a switch is connected. The implementation system comprises a reference source, a resistance voltage division circuit, a first RC passive low-pass filtering circuit, a power supply, a second RC passive low-pass filtering circuit, an active low-pass filtering circuit consisting of an operational amplifier, serially connected resistors, a high-capacity ceramic capacitor and an image sensor. The implementation system uses a topological structure that the operational amplifier follows after voltage division of an existing high-voltage reference source, the load capacitors of the switch inside the high-capacity ceramic capacitor and the image sensor are used to be connected in parallel to reduce the fluctuation of reference voltage, and external disturbance is reduced by using the low-pass filtering circuit.

The invention relates to a crystal oscillating circuit, which comprises an oscillating stage circuit, a direct current negative feedback circuit, and a push-pull amplifier circuit. The oscillating stage circuit generates an oscillator signal and outputs the oscillator signal to the direct current negative feedback circuit; the direct current negative feedback circuit performs amplitude control on the oscillator signal of the oscillating stage circuit and feeds back the oscillator signal to the oscillating stage circuit; the oscillating stage circuit outputs the oscillator signal which is subjected to the amplitude control to the push-pull amplifier circuit by the direct current negative feedback circuit; and the push-pull amplifier circuit is a post-stage amplifying circuit, amplifies the oscillator signal which is input and subjected to the amplitude control and outputs the oscillator signal to the outside. According to the invention, a transistor V5 adopts an emitter follower, so that an output load of the crystal oscillating circuit is less, and oscillation starting of the crystal is facilitated; and the capacitance of a capacitor which is connected in series with the crystal is increased, so that the capacitive reactance of the capacitor in the circuit is reduced, an alternating current which runs through the crystal is increased, and the driving power of the crystal is increased.

The invention relates to a method comprising the following steps:—measuring (S1) a traffic load;—determining (S2), if the traffic load is lower than a first threshold;—decreasing (S3) a maximum used output load of an amplifier of the base station, if the traffic load is lower than the first;—adjusting (S4) an operation point (102; 104; 106; 108; 112; 114; 116; 118; 124) of the amplifier, if the traffic load is lower than the first threshold;—determining (S2), if the traffic load is higher than a second threshold;—increasing (S5) the maximum used output load of the amplifier, if the traffic load is higher than the second threshold; and—adjusting (S4) the operation point of the amplifier, if the traffic load is higher than the second threshold.

An image reading apparatus is composed of an image input unit for obtaining multi-valued image data by reading an image optically; an image processing unit for performing image processing including screen processing on the multi-valued image data obtained by the image input unit; a data converting unit for converting image data obtained by the image processing of the image processing unit into a form that is described in a page description language; and an image output unit for outputting image data obtained by the conversion of the data converting unit to the outside.