79 results about "Quadrature voltage controlled oscillator" patented technology

A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.

The invention discloses a high-energy-efficiency low-jitter single loop clock data recovery circuit. The circuit comprises an 1/N rate Bang-Bang phase discriminator with a 1:N demultiplexer function, a voltage-current converter, a loop filter and a multi-phase clock generator. An orthogonal clock signal generated by an orthogonal voltage control oscillator in the multi-phase clock generator is synthesized into a needed (N+2) phase recovery clock signal through a cascaded digital phase interpolator. And then the 1/N rate Bang-Bang phase discriminator receives input data and a phase clock signal, detects a phase relationship between the two to generate a lead/lag voltage signal and recovers N paths of parallel 1/N rate data signals. Then, the lead/lag voltage signal is converted into a current signal through the voltage-current converter. A current passes through loop filter filtering and then controls an output clock frequency and a phase relationship of the multi-phase clock generator so as to reduce a frequency deviation so that phase locking of a clock data recovery loop is reached. Jitter performance of the clock data recovery loop is effectively improved.

A divide by X.5 circuit can be implemented as a divided by 1.5 circuit. A phase-locked loop (PLL) has a quadrature voltage-controlled oscillator (VCO) that generates four phases offset at 0, 90, 180, and 270 degrees. Differential signals from the VCO are converted to single-ended VCO clocks that drive four divide-by-3 circuits, each clocked by one of the four phases of the VCO clocks. Resets to the divide-by-3 circuits are staggered to activate each divide-by-3 circuit synchronously with its phase clock. Outputs from the divide-by-3 circuits are applied to a frequency doubler that generates the final clock that is 1.5 times slower than the VCO clocks. The final clock has a near 50%-50% duty cycle.

According to embodiments of the present invention, a quadrature voltage controlled oscillator is provided. The quadrature voltage controlled oscillator includes a first voltage controlled oscillator and a second voltage controlled oscillator respectively comprising an inductor having a first terminal and a second terminal, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor respectively comprising a first terminal and a second terminal, a first transistor, a second transistor, a third transistor and a fourth transistor respectively comprising a source terminal, a drain terminal and a gate terminal, wherein the first terminal of the inductor is coupled to the first terminal of the first capacitor, and the second terminal of the inductor is coupled to the second terminal of the first capacitor, wherein the drain terminal of the first transistor is coupled to the first terminal of the inductor, the first terminal of the first capacitor, the first terminal of the second capacitor, and the gate terminal of the fourth transistor, wherein the drain terminal of the second transistor is coupled to the second terminal of the inductor, the second terminal of the first capacitor, the first terminal of the third capacitor, and the gate terminal of the third transistor, wherein the source terminal of the first transistor is coupled to the second terminal of the second capacitor, the drain terminal of the third transistor, and the first terminal of the fourth capacitor, wherein the source terminal of the second transistor is coupled to the second terminal of the third capacitor, the drain terminal of the fourth transistor, and the second terminal of the fourth capacitor, wherein the gate terminal of the first transistor of the first voltage controlled oscillator is directly coupled to the first terminal of the inductor of the second voltage controlled oscillator, wherein the gate terminal of the second transistor of the first voltage controlled oscillator is directly coupled to the second terminal of the inductor of the second voltage controlled oscillator, wherein the gate terminal of the first transistor of the second voltage controlled oscillator is directly coupled to the second terminal of the inductor of the first voltage controlled oscillator, wherein the gate terminal of the second transistor of the second voltage controlled oscillator is directly coupled to the first terminal of the inductor of the first voltage controlled oscillator.

According to some embodiments, unilateral coupling is provided for a quadrature voltage controlled oscillator. For example, a first voltage controlled oscillator may be provided with a 0 degree phase node and a 180 degree phase node A second voltage controlled oscillator may be provided with a 90 degree phase node and a 270 degree phase node. In addition, the first and second voltage controlled oscillators may be mutually coupled with substantially unilateral cascaded common-source common-gate amplifier coupling devices to create a quadrature voltage controlled oscillator.

The invention belongs to the technical field of radio frequency wireless receiver integrated circuits, and relates to a quadrature voltage controlled oscillator in a wireless receiver integrated circuit. In the quadrature voltage controlled oscillator, the phase noise performance of the quadrature voltage controlled oscillator circuit is improved and the output phase mismatch is reduced by improving a coupling mode of the conventional quadrature voltage controlled oscillator and introducing a phase shift network at the source end of a coupling tube. By using a linearly changed an accumulation-type metal-oxide semiconductor (MOS) variable capacitor array, the linearity of a tuning curve of a quadrature voltage controlled oscillator (QVCO) is greatly improved so that the tuning range of a control voltage is increased. Because a bias current of the QVCO is variable, a relatively constant output oscillating voltage amplitude can be maintained; therefore, a low phase noise can be obtained by the QVCO in a broad output frequency range.

Disclosed is a quadrature VCO (voltage controlled oscillator) which comprises a first delay cell including a first switching transistor and a second switching transistor, the first delay cell outputting first and second in-phase signals with different phases; and a second delay cell including a third switching transistor and a fourth switching transistor, the second delay cell outputting first and second quadrature-phase signals with different phases. The first and second quadrature-phase signals are applied to back gates of the first and second switching transistors, and the first and second in-phase signals are applied to back gates of the fourth and third switching transistors.

A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.

A quadrature voltage controlled oscillator includes oscillation circuits for generating in-phase and quadrature-phase oscillation signals that are used to generate in-phase and quadrature-phase output signals. A compensation circuit adjusts biasing in the oscillation circuits depending on a phase relationship between the in-phase and quadrature-phase output signals to automatically control the phase relationship between the oscillation signals.

In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

The invention discloses a frequency synthesizer used in orthogonal frequency division multiplexing ultra-wideband (OFDM UWB). The frequency synthesizer adopts a phase-locked loop (PLL) structure basedon integer frequency division and consists of a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a quadrature voltage controlled oscillator (QVCO) and a 64-127 multi-modulus frequency divider which are connected in turn, wherein the PFD is connected with the 64-127 multi-modulus frequency divider at the same time to ensure that the PFD, the CP, the LPF, the QVCO and the 64-127 multi-modulus frequency divider are formed into the PLL structure. The frequency synthesizer provided by the invention can generate OFDM UWB local-oscillation signals of 10 frequency points including 4,356M, 4,620M, 6,336M, 6,600M, 6,864M, 7,128M, 7,392M, 7,656M, 7,920M, 8,184M, and the like, thereby realizing high frequency and wide frequency band and meeting the requirements of being applied in OFDM UWB.

The invention belongs to the technical field of simulated radio frequency integrated circuits, in particular to an accurate quadrature voltage-controlled oscillator capable of achieving phase adjusting and capable of being applied to a radio frequency synthesizer integrated circuit. The circuit is mainly an injection-locking quadrature voltage-controlled oscillator. The injection-locking quadrature voltage-controlled oscillator is composed of a negative resistance network, an on-chip inductance-capacitance resonant cavity, a voltage-controlled variable capacitor and an adjustable biasing circuit. The quadrature voltage-controlled oscillator is composed of two injection-locking quadrature voltage-controlled oscillator units, coupling of signals of the injection-locking quadrature voltage-controlled oscillator is carried out through a series injection mode, and the purpose of outputting quadrature signals is achieved. The adjustable biasing circuit comprises current bias of the quadrature voltage-controlled oscillator and DC voltage bias of quadrature signal coupling injection. By adjusting the bias currents and the bias voltages, the phases of the output signals are made to be adjustable, phase errors caused by fabrication errors, device adaptation and the like can be corrected, and accurately output quadrature signals can be obtained.

In a quadrature voltage controlled oscillator, a first oscillator includes a first resonant circuit for generating a preset first resonant frequency and a first pair of cross-coupled transistors for supplying energy to the first resonant frequency to generate first and second signals having a phase difference of 180°. A second oscillator includes a second resonant circuit for generating a preset second resonant frequency and a second pair of cross-coupled transistors for generating third and fourth signals for supplying energy to the second resonant frequency having a phase difference of 180°. A first current source is connected between a first common node of the first cross-coupled transistor pair and a ground. A second current source is connected between a second common node of the second cross-coupled transistor pair and the ground. A differential load is connected between a third common node of the first and second current sources and the ground.

The invention discloses a digital phase-locked loop frequency synthesis device. The device comprises an orthogonal voltage-controlled oscillator, an output buffer, an eight-division frequency-divider,a phase interpolator, a digital processor, a digital time converter, a sampler, an analog-to-digital converter, a digital loop filter, a digital-to-analog converter and a frequency locking module. The digital phase-locked loop frequency synthesis device disclosed by the invention can generate 28-32 GHz continuous coverage millimetre-wave orthogonal signal output, and can satisfy the local oscillation requirement of a transceiver in the frequency band; furthermore, voltage signals are converted into digital signals through the analog-to-digital converter; the equivalent time resolution is improved; the in-band phase noise of output signals is improved; the required delay coverage range of the digital time converter is reduced; the linearity of the digital time converter is improved; and the spurious performance of output signals is improved.

The invention discloses a low-noise high-precision broadband multiphase clock generator characterized by comprising a broadband quadrature voltage-controlled oscillator, a voltage-controlled oscillator output buffer, and an adjustable digital phase interpolator. The low-noise high-precision broadband multiphase clock generator generates a multiphase clock signal by using a compact open-loop architecture in which the broadband quadrature voltage-controlled oscillator and the adjustable digital phase interpolator are in cascaded connection, prevents problems in lock delay, stability, and phase precision due to closed-loop feedback structure and complex control logic, and eliminates an extra reference clock.

Multiple carrier frequencies are provided from a phase locked loop, especially closely adjacent quadrature amplitude modulated subcarriers for multiplexed data communications. A quadrature voltage controlled oscillator (VCO) and cascaded frequency dividers provide feedback to a phase comparator to lock the VCO to a reference signal. In addition to frequency divider outputs for use as subcarriers, e.g., binary division factors of the VCO frequency, a quadrature mixer multiplies and adds corresponding quadrature components at two of the frequencies, to generate a differential signal at a difference frequency. The mixer may be outside of the feedback signal path but preferably is in the feedback path to suppress noise. A polyphase filter converts the mixer output to a quadrature signal useful as a subcarrier. The technique efficiently generates sequential integer multiples of a basic frequency, such as sixteen adjacent integer multiples of a frequency reference.

A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Provided is a colpitts quadrature voltage controlled oscillator capable of obtaining quadrature orthogonal signals using a quadrature combination between a base and a collector of each transistor, without using an additional circuit such as a coupled transistor, a coupled transformer, a multiphase RC filter, etc. Accordingly, since nonlinearity, increased phase noise, a decrease in the Q-factor of an LC resonator, and increased power consumption can be avoided, a colpitts quadrature voltage controlled oscillator that has low phase noise, low electric power consumption, and a compact size can be implemented.

The invention discloses a near-threshold low-power-consumption quadrature voltage controlled oscillator. The voltage controlled oscillator comprises an oscillator main body circuit and a self-detection bias circuit, wherein a phase coupling circuit in the oscillator main body circuit and a peak value detection circuit in the self-detection bias circuit are combined, so that current is multiplexed, and the power consumption is lowered. The near-threshold low-power-consumption quadrature voltage controlled oscillator works under a relatively high bias voltage at the beginning of oscillation start, and oscillation of the circuit can be started rapidly under large current. After oscillation start, four PMOS (P-channel Metal Oxide Semiconductor) transistors limit phase differences among four paths of oscillation signals at 90 degrees, detect a peak voltage and control the bias circuit to lower a bias point, so that the power consumption is lowered, and the noise performance is optimized.