Low-noise high-precision broadband multiphase clock generator

Abstract

The invention discloses a low-noise high-precision broadband multiphase clock generator characterized by comprising a broadband quadrature voltage-controlled oscillator, a voltage-controlled oscillator output buffer, and an adjustable digital phase interpolator. The low-noise high-precision broadband multiphase clock generator generates a multiphase clock signal by using a compact open-loop architecture in which the broadband quadrature voltage-controlled oscillator and the adjustable digital phase interpolator are in cascaded connection, prevents problems in lock delay, stability, and phase precision due to closed-loop feedback structure and complex control logic, and eliminates an extra reference clock.

Description

technical field [0001] The invention relates to the technical fields of high-speed communication and analog radio frequency integrated circuits, in particular to a low-noise and high-precision broadband multiphase clock generator. Background technique [0002] The multiphase clock generator (MPCG) is widely used, such as in harmonic suppression mixer (mixer) and multipath multiphase circuit to suppress unwanted harmonics and sideband signals, in time-interleaved analog-to-digital converter ( ADC) is used to sample higher frequency analog signals, and is used to process higher bit rate received data in the sub-rate clock data recovery circuit (CDR). Considering the modern high-speed application environment and the performance impact on the application circuit, for example, the quadrature mismatch of the local oscillator signal in the wireless transceiver will introduce additional image interference signals, thereby reducing the signal-to-noise ratio of the wireless receiver; ...

AI Technical Summary

Problems solved by technology

The structure is a first-order system, which is easy to design and easy to ensure system stability; based on the DLL structure, the voltage-controlled delay chain (VCDL) is used to replace the QVCO based on the PLL structure, which avoids the problem of jitter accumulation; using multiple delay units (Delay Unit ) can generate multi-phase clock signals, but as the number of required multi-phase clocks increases, the output frequency will decrease accordingly, and there is inevitably a mismatch problem between multiple Delay Units, which cannot meet the high-speed application (has reached 10Gbps or even higher) and high-precision phase requirements

[0006] The multi-phase clock generator structure in the above-mentioned related art usually needs to utilize a feedback loop and a large-area loop filter (LF) and an external reference clock (Ref_Clk), and there are always loop stability, complex design and on-chip integration And multi-channel phase accuracy and other issues

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