46results about How to "Reduce propagation delay" patented technology

A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CK_in and generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (t_pd) between the toggling of CK_in and a resulting change at the slave latch's output less than it would otherwise be.

A method of fabricating an electrical connection for a spatial light modulator includes providing a first substrate including a plurality of bias electrodes and a plurality of dielectric bond pads. The method also includes providing a second substrate of a predetermined thickness, the second substrate including a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff region, and joining the dielectric bond pads of the first substrate to the standoff region of the second substrate. The method further includes forming mirror structures from a first portion of the second substrate, exposing a portion of the upper surface of the plurality of bias electrodes, and depositing a conductive layer on the mirror structures and the exposed portion of the upper surface of the plurality of bias electrodes.

The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for controlling the propagation of a selected input signal through the pass gates of the multiplexer circuit. For some embodiments, some of the select signals may be decoded to generate a number of decoded select signals that can be used to control the selective routing of signals through the multiplexer.

The invention discloses a lossless switching method for inter-satellite data of low-orbit satellites, which specifically comprises the following steps that: S1, a user terminal sends a measurement report to a network controller according to the generated measurement report, S2, the network controller executes switching judgment, if switching can be carried out, S3 is executed, and if switching cannot be carried out, S4 is executed, S3, it is judged whether the target satellite resources are allowed to be switched or not, if yes, S5 is executed, and if not, S4 is executed, S4, switching is notcarried out, S4', it is judged whether the user terminal of which the signal stays on the original satellite has a switching continuing demand or not, if so, S1 is executed, and if not, the switchingaction is stopped, S5, the target satellite allocates channel resources to the allowed user terminal, and sends a switching request instruction to the terminal through the service satellite, S6, the terminal receives the switching request and sends switching success information to the target satellite, S7, the network controller immediately releases the temporary storage data and S8, switching iscompleted. The device has the advantages of being simple in structure, smooth in network access and small in loss.

The invention discloses a flight delay causality network building method based on a Granger test, pertaining to the technical field of delay analyses for civil aviation. The method comprises the following steps: firstly, acquiring a delay time sequence of each airport with the set time period according to historical data of flight of airports; then, taking each airport as a node for the network and testing a Granger causality of each pair of airports, when an airport I causes delay of an airport j by the test and establishing a directed edge from a node i to node j; and ultimately, repeating the above processes till selected airports are added to the network and making flight delay analyses by means of the obtained network. Through the established flight delay causality network, the numberof delay dissemination paths is analyzed for some large airports. Therefore, the delay dissemination range is narrowed, thereby effectively resolving a delay problem. The delays disseminated by an overall system are reduced. Therefore, loss caused by many flight delays is lowered.

A new partial product bit generator is used to generate a partial product bit PPj_i. In some embodiments, the partial product bit generator generates the partial product bit PPj_i from intermediate signals that are able to be generated concurrently, for example in two levels of combinatorial logic. The partial product bit PPj_i is then able to be generated from the intermediate signal, for example in only one level of combinatorial logic. In such embodiments, a long series of combinatorial logic operations is not required.

Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.

A nonvolatile memory device includes a memory cell array and a peripheral circuit. The peripheral circuit is connected to the memory cell array through conductive lines and includes transistors. Each of the transistors is formed on the substrate and includes first and second regions and a gate electrode. In at least one of the transistors, the first region is connected to at least one of the conductive lines through first contact plugs extending in the direction perpendicular to the substrate, and second contact plugs extending in the direction perpendicular to the substrate. A contact area of each of the first contact plugs is different from a contact area of each of the second contact plugs.

A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a voltage value approximately near a threshold voltage of the control circuit. The pre-charge bias amount is slightly less than the amount needed to place the control circuit in a high current conduction state. A coupling circuit is thereafter used and adapted to couple an input voltage applied to the buffer circuit to the input of the control circuit. This causes the control circuit to enter the high current conduction state. Depending on the input impedance of the coupling circuit, by pre-charging the coupling circuit input, less time is needed to cause the coupling circuit to enter and thereafter leave a high current conduction state. Therefore, by pre-charging the coupling circuit, output transitions from the buffer circuit can be accelerated and propagation delay reduced. The pre-charge circuit and the control circuit operate on one or more stages of a single or multi-stage buffer, operate on single-ended or differential/complementary input/output, and operate to speed up either the rising, falling, or both edges transitions at the output of the buffer.

Various embodiments set forth systems and techniques for concurrent log and dump processing. The techniques include selecting, from a datastore, a chunk comprising one or more rows of data; comparing the one or more rows of data in the chunk with a first set of log events in a change log associated with the datastore, wherein each log event included in the first set of log events occurs after a first log event in the change log and prior to a second log event in the change log; selecting, based on the comparison, one or more non-conflicting rows in the chunk; and transmitting, to an output, one or more log events associated with the one or more non-conflicting rows in the chunk prior to processing a second set of log events in the change log, wherein the second set of log events occur after the second log event.

The invention discloses practical system-level redundant communication network architecture. Switches of a backbone network of the network architecture adopt a VSS (Virtual Switching System) technology to realize redundancy, two mutually redundant network switches are equivalent to virtual machines and have the same IP (Internet Protocol) address, so that fault switching can be realized in the shorter time; when the virtual switches carry out data communication, IP switching and judgment of the switches are not needed, so that occupation of resources, such as a CPU (Central Processing Unit) and an internal storage, can be effectively reduced; in addition, the network topology is simplified from the logical level through the VSS technology, and the mutually redundant network switches share one gateway address, so that loop-less communication is realized and the reliability of a communication network system can be effectively improved; an optical fiber for connecting a front-end switch and a back-end switch of the backbone network adopts a GEC (Gigabit Ethemet Channel) technology to bind one Ethernet channel, so that the data transmission bandwidth of the communication network can be effectively widened and the information throughput rate can be improved, and thus the propagation delay for front-end communication and back-end communication is reduced.

Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select signals. The propagation delay of the output signal is reduced by using a first voltage source to drive the input signals and the output signal and a second voltage source, having a higher voltage than the first voltage source, to drive the select signals. The higher voltage source reduces the impedance of each transistor driven by the select signals, thus reducing the propagation delay at the output of the phase mixer. For a non-differential digital phase mixer, the propagation delay is reduced in the rising edges of the output signal. For a differential digital phase mixer, the propagation delay is reduced in the rising and falling edges of the output signal.

The embodiment of the invention provides a channel transmission method and communication equipment. The method comprises the following steps: determining a transmission beam corresponding to a monitoring position MO in a monitoring window of a downlink control channel; and transmitting the downlink control channel on the MO according to the transmission beam corresponding to the MO. Thus, when thetransmission beam changes, the propagation delay of the downlink control channel can be reduced, and the transmission reliability of the downlink control channel can be improved.

A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

The invention discloses a space-ground integrated fusion network, which comprises a core network and communication satellites. The space-ground integrated fusion network comprises the core network and the plurality of communication satellites, wherein the core network performs routing selection on a set formed by a first communication satellite group and a second communication satellite group, and the plurality of communication satellites determined by the routing selection initiate paging to a satellite terminal, the first communication satellite group and the second communication satellite group respectively comprise at least one communication satellite, an elevation angle of the communication satellite in the first communication satellite group relative to the core network is maximum, and an elevation angle of the communication satellite in the second communication satellite group relative to the satellite terminal is maximum. According to the space-ground integrated fusion network, the reliability of all available communication satellites is considered globally, on one hand, the advantages of acquiring the shortest topological path and the like of a routing selection algorithm can be played, and the properties of channel bandwidth, average communication traffic, communication overhead, queue length, propagation delay and the like of routing can be improved. The space-ground integrated fusion network is widely applied to the technical field of satellite communication.

A driver device is for switching on and off a transistor for supplying a load by driving a control electrode of the transistor. The driver device includes a first terminal connected to the control electrode of the transistor, a second terminal connected between the transistor and the load, and a current-discharge path coupled to the first terminal. The current-discharge path includes a diode and is activated when the transistor is switched off. The diode becomes non-conductive to interrupt the current-discharge path when the voltage on the second terminal reaches a threshold value.

The present invention is directed to communication systems and methods thereof. More specifically, an embodiment of the present invention includes a buffer that is coupled to a reference terminal. A shift register stores decision levels for post-cursor positions. A plurality of switches converts the decision levels to equalization currents during an equalization process. The equalization currents are converted to equalization voltage terms by one or more load resistors. The buffer is provided between the reference terminal and the one or more load resistors. There are other embodiments as well.

Oscillator and electronic device comprising an oscillator, wherein the oscillator has an RC-circuit and a push-pull stage. A tapping point of the RC-circuit is coupled to an input of the push-pull stage and an output of the push-pull stage is fed back to a switching transistor which is coupled to the tapping point of the RC-circuit.

Disclosed is a transimpedance amplifier, comprising a first-stage trans-conductance amplifier TCA, a second-stage TCA, a third-stage amplifier and a feedback circuit. The first-stage TCA is electrically connected to an input current source to receive a first input signal, and outputs a first output signal. The second-stage TCA is electrically connected to the first-stage TCA to receive the first output signal, and outputs a second output signal. The third-stage amplifier is electrically connected to the second-stage TCA to receive the second output signal, and outputs a third output signal. One end of the feedback circuit is electrically connected to the input of the first-stage TCA, and the other end of the feedback circuit is electrically connected to the output of the third-stage amplifier to stabilize the third output signal. The third-stage amplifier is composed of a first output stage and a second output stage.

A method and apparatus for testing shield continuity are provided. In the method and apparatus, a transmitter transmits a first signal in common mode over a plurality of conductors of a cable or cabling installation having a shield. The first signal is transmitted in the common mode at a first end of the plurality of conductors. A receiver receives a plurality of second signals representative of the first signal at a second end of the plurality of conductors, respectively, and outputs data representative of the plurality of second signals. A processor receives the data representative of the plurality of second signals, determines a common mode insertion loss for the cable or cabling installation based on the plurality of second signals, determines, based on the common mode insertion loss, whether the shield is continuous or discontinuous and outputs data representative of whether the shield is continuous or discontinuous.

A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.