Clock dynamic switching circuit

Abstract

The invention relates to the technical field of circuit design, in particular to a clock dynamic switching circuit. The circuit comprises a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clockgating circuit and an OR gate circuit. The level synchronization circuit is used for synchronizing the first clock enable signal line and a first clock signal and synchronizing the second clock enable signal line and a second clock signal, and the clock gating circuit is used for controlling on-off of the clock signals. According to the circuit, the positive edge of the clock is used for triggering all devices in the circuit, a half-cycle path does not exist any more, the highest operation frequency of the circuit is improved, clock glitch is avoided through a feedback mechanism, and signalsoutput by the circuit are free of burrs.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to a clock dynamic switching circuit. Background technique [0002] There are usually multiple clocks with different frequencies in the chip, and when they are applied in different power consumption modes, the clocks will be dynamically switched according to the needs. For example, when the chip is running at low power consumption, the clock is switched to a low-frequency clock; when the chip is running at full power, the clock is switched to a high-frequency clock. The frequencies of the high-frequency and low-frequency clocks may not be related, or they may be multiples. The problem that needs to be paid attention to during dynamic clock switching is that clock glitch (glitch) (see Note 1) should be avoided during dynamic clock switching. If an unexpected clock glitch occurs, it may cause fatal abnormal errors on the chip (see Note 1). 2), which is absolutely not allowed ...

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Problems solved by technology

[0004] Note 2: The digital circuit has a limit on the maximum operating clock frequency, and can only run stably at a frequency less than or equal to the maximum clock frequency. If an unexpected clock glitch occurs, it means that the frequency of the current clock glitch is higher than the preset clock frequency in the circuit. exception will occur

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