FFT processor data storage system and method

A data storage system and processor technology, applied in the field of digital mobile communication, can solve the problem of increasing the area of ​​hardware resources, and achieve the effect of small area and high utilization rate

Active Publication Date: 2008-10-22
MAXSCEND MICROELECTRONICS CO LTD
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the use of dual-port memory in this method, in the implementation of integrated circuits, the memory...

Method used

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  • FFT processor data storage system and method
  • FFT processor data storage system and method
  • FFT processor data storage system and method

Examples

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Embodiment Construction

[0019] An example of a radix-2FFT processor at N points is given below. In the radix-2FFT operation, there are log 2 N levels, the number of butterfly operations per level is N / 2.

[0020] Such as image 3 As shown, the data storage system of the FFT processor of the present invention includes a controller, a butterfly operation unit, a data memory, and a twiddle factor table. The controller includes a butterfly operation counter, a stage counter, an index number generator, an address mapper, a delay unit, and a twiddle factor sequence number generator.

[0021] The butterfly operation counter indicates the serial number of the butterfly operation in each stage, the counting range is from 0 to N / 2-1, the butterfly operation counter is incremented by one every clock cycle, and restarts from 0 after counting to N / 2-1 . Counting in binary, the butterfly operation counter needs m-1 bits, where m=log 2 N, the counting result is recorded as count[m-2:0].

[0022] The series cou...

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Abstract

The invention discloses a system and a method for data storage of an FFT processor. The data storage system comprises a controller, a storage, a papilionaceous operation unit and a twiddle factor form; the storage is used for storing data; the twiddle factor form stores a twiddle factor needed for each papilionaceous operation according to the sequence; the papilionaceous operation unit is used for the papilionaceous operation; the controller comprises a papilionaceous operation counter, a series counter, an index number generator, an address mapping device, a delay unit and a twiddle factor serial number generator; the data storage method comprises the following steps that: according to the input sequence, input data is recorded as dindex, wherein, the index is equal to 0, 1, ..., N-1; the index is represented by a binary digit and needs m bits, wherein, the m is equal to log 2N, that is, recorded as index[m-1:0]; and the input data is stored in the storage. The system and the method for data storage of the FFT processor use a single-port storage to realize the conflict-free read-write access; and the utilization rate of the papilionaceous operation unit is nearly 100 percent, thereby effectively improving the utilization efficiency of hardware resource.

Description

technical field [0001] The invention relates to the field of digital mobile communication, in particular to a data storage system of an FFT processor. The invention also relates to a method of data storage using an FFT processor. Background technique [0002] In digital signal processing, discrete Fourier transform (Discrete Fourier TransformDFT) is a mathematical tool to describe the relationship between time domain and frequency domain of discrete signals. Fast Fourier Transform (FFT) is a fast algorithm to reduce the computational complexity of DFT, and it plays an important role in various digital signal processing systems. To calculate the FFT of an N-point base r, that is, the FFT with r as the base, you need to have (N / r)log r N butterfly operations and 2Nlog r N data access operations. [0003] FFT processors usually have two structures, one is a cascaded structure (such as figure 1 shown), the other is a single-level structure (such as figure 2 shown). The b...

Claims

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Application Information

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IPC IPC(8): G06F17/14
Inventor 张卓鹏
Owner MAXSCEND MICROELECTRONICS CO LTD
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