FFT processor data storage system and method

Abstract

The invention discloses a system and a method for data storage of an FFT processor. The data storage system comprises a controller, a storage, a papilionaceous operation unit and a twiddle factor form; the storage is used for storing data; the twiddle factor form stores a twiddle factor needed for each papilionaceous operation according to the sequence; the papilionaceous operation unit is used for the papilionaceous operation; the controller comprises a papilionaceous operation counter, a series counter, an index number generator, an address mapping device, a delay unit and a twiddle factor serial number generator; the data storage method comprises the following steps that: according to the input sequence, input data is recorded as dindex, wherein, the index is equal to 0, 1, ..., N-1; the index is represented by a binary digit and needs m bits, wherein, the m is equal to log 2N, that is, recorded as index[m-1:0]; and the input data is stored in the storage. The system and the method for data storage of the FFT processor use a single-port storage to realize the conflict-free read-write access; and the utilization rate of the papilionaceous operation unit is nearly 100 percent, thereby effectively improving the utilization efficiency of hardware resource.

Description

technical field [0001] The invention relates to the field of digital mobile communication, in particular to a data storage system of an FFT processor. The invention also relates to a method of data storage using an FFT processor. Background technique [0002] In digital signal processing, discrete Fourier transform (Discrete Fourier TransformDFT) is a mathematical tool to describe the relationship between time domain and frequency domain of discrete signals. Fast Fourier Transform (FFT) is a fast algorithm to reduce the computational complexity of DFT, and it plays an important role in various digital signal processing systems. To calculate the FFT of an N-point base r, that is, the FFT with r as the base, you need to have (N / r)log r N butterfly operations and 2Nlog r N data access operations. [0003] FFT processors usually have two structures, one is a cascaded structure (such as figure 1 shown), the other is a single-level structure (such as figure 2 shown). The b...

AI Technical Summary

Problems solved by technology

Due to the use of dual-port memory in this method, in the implementation of integrated circuits, the memory area is about twice the volume of single-port memory, which greatly increases the area of ​​​​hardware resources.

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