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FFT architecture and method

A multiplier and memory technology, applied in the field of signal processing, can solve the problems of reducing processing power and insufficient processing power

Inactive Publication Date: 2007-02-14
QUALCOMM INC
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

In many systems, the amount of processing power dedicated to performing DFT reduces the amount of processing power available for other system operations
Furthermore, systems operating in real-time may not have sufficient processing power to perform a DFT of the expected size in the time allotted for computation

Method used

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  • FFT architecture and method

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Embodiment Construction

[0020] The present application discloses a hardware structure suitable for FFT or inverse FFT (IFFT), a device integrating the FFT module, and a method for performing FFT or IFFT. The FFT structure is generic so that any radix FFT can be implemented. This FFT structure minimizes the number of cycles used to perform the FFT while keeping the chip area small. Specifically, the FFT architecture configures memory and register space to facilitate optimization of memory accesses when performing in place FFTs. This FFT structure provides additional implementation flexibility, allowing for different numbers of radix and complex multipliers depending on specific design constraints. In speed-sensitive implementations that are less sensitive to die area, the FFT structure can be implemented with additional complex multipliers and higher radix. In implementations that are more sensitive to die area, the number of radix and complex multipliers can be reduced.

[0021] The FFT structure ...

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Abstract

A Fast Fourier Transform(FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit(IC). The FFT hardware can implement an N point FFT, where N = rn is a function of a radix(r). The hardware implementation includes a sample memory having N / r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0 < k G06F 17 / 14 8 18 8 2004 / 12 / 3 1914607 2007 / 2 / 14 000000000 Qualcomm Inc. United Krishnamoorthi Raghuraman Ganapathy Chinnappa K. wang yang 72002 NTD Patent & Trademark Agency Ltd. Units 1805-6, 18th Floor, Greenfield Tower, Concordia Plaza, No.1 Science Museum Road, Tsimshatsui, east, Kowloon, Hong Kong 100045 United 2003 / 12 / 5 60 / 527,196 2006 / 8 / 4 PCT / US2004 / 040498 2004 / 12 / 3 WO2005 / 057423 2005 / 6 / 23 English

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority to US Provisional Application No. 60 / 527,196, filed December 5, 2003, entitled "NOVELARCHITECTURE FOR IMPLEMENTING HIGHSPEED FFTS INHEARDWEAR," which is incorporated herein in its entirety. Field of Invention [0003] The present disclosure relates to the field of signal processing, and in particular, to an apparatus and method for implementing Fast Fourier Transform (FFT). technical background [0004] The Fourier transform can be used to map a time-domain signal to its frequency-domain counterpart. Conversely, the inverse Fourier transform can be used to map a frequency-domain signal to its time-domain counterpart. The Fourier transform is especially useful for spectral analysis of time-domain signals. Additionally, communication systems, such as those implementing Orthogonal Frequency Division Multiplexing (OFDM), can exploit the properties of the Fourier transform to generate multi...

Claims

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Application Information

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IPC IPC(8): G06F17/14G06F15/00H04L27/26
CPCG06F17/142H04L27/265H04L27/2651G06F17/14
Inventor 拉古拉曼·克里希纳姆尔蒂钦纳帕·K·加纳帕蒂
Owner QUALCOMM INC
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