Point-changeable floating point FFT (fast Fourier transform) processor

Abstract

The invention relates to a point-changeable floating point FFT processor. The point-changeable floating point FFT processor comprises a data selection and storage module, butterfly calculation units and a rotating factor storage, wherein the data selection and storage module is used for storing input data and outputting data required by the butterfly calculation unit according to the time domain radix-2 algorithm; when FFT points are selected to be 1024, externally input data are placed in order inside the RAM (random access memory) of the data selection and storage module, and when the FFT points are selected to be the others, the data are placed at intervals; the butterfly calculation units are used for completing the butterfly calculation of the FFT algorithm, and the number of the butterfly calculation units is four; the rotating factor storage is used for storing rotating factors required by the butterfly calculation units, and the address of the rotating factor storage is controlled by the data selection and storage module. The point-changeable floating point FFT processor comprises the four butterfly calculation units, thereby reducing the original calculation time by three quarters and achieving a calculation speed four times as high as that of IP (intellectual property) cores of the ALTERA corporation, and meanwhile due to the fact that the points can be selected to be 32, 64, 128, 256,612 or 1024, achieves point configurability and use flexibility.

Description

technical field [0001] The invention relates to the technical field of digital signal processing and integrated circuit design, in particular to a variable-point floating-point FFT processor. Background technique [0002] In weather radar signal processing, fast Fourier transform is a commonly used algorithm. Due to its complexity, it is generally implemented in a DSP processor, but to implement it in a DSP processor requires an additional DSP processor on the circuit board. Moreover, due to the limitation of the operating speed of the DSP processor, parallel computing cannot be realized. [0003] In order to improve the integration of system hardware, save cost, and increase the operation speed, it is a better solution to implement FFT processing in the FPGA controller. However, it will consume quite a lot of resources to implement in the FPGA controller. Property rights) nuclear, but also need to purchase the corresponding license. [0004] The number of FFT calculation ...

AI Technical Summary

Problems solved by technology

[0002] In weather radar signal processing, fast Fourier transform is a commonly used algorithm. Due to its complexity, it is generally implemented in a DSP processor, but to implement it in a DSP processor requires an additional DSP processor on the circuit board. Moreover, due to the limitation of the running speed of the DSP processor, parallel computing cannot be realized.

[0003] In order to improve the integration of system hardware, save cost, and increase the operation speed, it is a better solution to implement FFT processing in the FPGA controller. However, it will cons...

Images