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FFT processor with pipeline structure

A processor and pipeline technology, which is applied in the field of signal processing, can solve the problems of large storage overhead of FFT processors, and achieve the effects of reducing storage overhead, saving chip area, and reducing storage space

Active Publication Date: 2013-07-31
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0004] In view of this, the main purpose of the present invention is to provide a FFT processor with a pipeline structure, to solve the problem of large storage overhead in the FFT processor with a pipeline structure in the prior art

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Embodiment Construction

[0031] In order to make the above objects, features and advantages of the present invention more comprehensible, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0032] FFT can be divided into base 2, base 4, base 8, and base 2 according to the operation base r. 4 etc. Each algorithm is different in the structure of a single operation unit, that is, the number of data points calculated by each unit is different. According to the law of operation extraction, it can be divided into two categories, namely, Decimation In Time (DIT) and Decimation In Frequency (DIF). Taking the radix-2-DIT-FFT algorithm as an example, the basic principle of the FFT based on the present invention is briefly described.

[0033] Let the length of sequence x(n) be N, N=2 M , M is a positive integer.

[0034] x 1 (r) and x 2 (r) is a subsequence of two N / 2 points decomposed by x(n)...

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Abstract

The invention discloses an FFT (Fast Fourier Transform) processor with a pipeline structure, which is used for processing an N-point r-DIT-FFT calculation, wherein the N equals to 2 <M>, and the M is a positive integer. The processor comprises L-level butterfly calculate units, a plurality of input storage units, and two output storage units, wherein the L equals to log r <N>; each level of butterfly calculate unit is connected with two input storage units; each level of the butterfly calculate unit is connected with the two input storage units of a next level of butterfly calculate unit except the Lth-level butterfly calculate unit; the Lth level butterfly calculate unit is connected with the two output storage units; storage spaces of two input storage units of a first-level butterfly calculate unit, and two input storage units and the two output storage units of the Lth level butterfly calculate unit are N point; and storage spaces of two input storage units of a Kth level butterfly calculate unit are r <K> point, wherein the K is a positive integer larger than one and less than L.

Description

technical field [0001] The invention relates to the technical field of signal processing, in particular to an FFT processor with a pipeline structure. Background technique [0002] The FFT (Fast Fourier Transformation, fast Fourier transform) algorithm is a fast algorithm of the DFT (Discrete Fourier Transform, discrete Fourier transform), which greatly reduces the computational load of the DFT algorithm. FFT is one of the main algorithms of digital signal processing. FFT processors are widely used in speech recognition, image processing and spectrum analysis. [0003] There are four main forms of FFT processor hardware implementation: sequential processing, pipeline processing, parallel processing and array processing. Adopting the pipeline structure is an important technical way to improve the speed of FFT operation. It can ensure that each level of operation in FFT can be performed simultaneously. When the input data rate matches, the total system operation time is only ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 张挺陈岚冯燕
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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