Method of realizing parallel structure for FFT processor based on FPGA

A processor and multiplier technology, applied in the field of FFT implementation, can solve problems such as insufficient flexibility, and achieve the effect of improving processing speed and system throughput

Inactive Publication Date: 2009-11-18
SHANGHAI BOOM FIBER SENSING TECH
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For example, literature (Ananth Gramam, AnshulGupta, George Karypi s.Introduction to ParallelComputing, SecondEdition[M], Pearson Education, Harlow, England, 2003: 245-250) men

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  • Method of realizing parallel structure for FFT processor based on FPGA
  • Method of realizing parallel structure for FFT processor based on FPGA
  • Method of realizing parallel structure for FFT processor based on FPGA

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[0012] The present invention theoretically analyzes and designs a parallel FFT processor structure based on FPGA—splits long sequences into shorter sequences, and realizes the FFT of short sequences in parallel by multiple FFT units, and finally uses a specific structure inside FPGA The calculation circuit of each unit is used to process the calculation results of each unit, so as to obtain the final result.

[0013] The method of implementing parallel structure FFT processor based on FPGA is used to perform N (N is the k power of 2, or less than the k power, and the sequence is filled with 0 to make N become the k power of 2, k is a positive integer) points The FFT operation, described FPGA comprises a plurality of dedicated multipliers, a plurality of a large number of block RAMs, and a plurality of logic gates, comprising the following steps:

[0014] (1) Dividing the N points into M segments equally, each segment having N / M points;

[0015] (2) the FFT operation of the N ...

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Abstract

The invention discloses a method of realizing parallel structure for FFT processor based on FPGA, which is used for FFT operation on N point. The FPGA comprises a plurality of special multipliers, a plurality of mass RAM and a plurality of logic gates. The method comprises the following steps: (1) dividing N point into M segments equally with N/M point on each segment; (2) translating FFT operation of N point into an expression of the FFT operation of the M segments (with N/M point on each segment); (3) extracting the coefficients of the expressions of FFT operation of M segment obtained in step (2), multiplying the coefficients with FFT operation results in corresponding M segment through FPGA inner circuit by using special multipliers, mass RAM and logic gates, and summing the product results of all segments to obtain FFT operation result of N point. By splitting a longer sequence into shorter sequences, the method in the invention effectively improves the processing speed of the long sequence FFT and system throughput.

Description

technical field [0001] The invention relates to a method for realizing FFT, in particular to a method for realizing a parallel structure FFT processor based on FPGA. Background technique [0002] Fast Fourier Transform (FFT, namely Fast Fourier Transform) has a very wide application in the field of digital signal processing, but the long-sequence FFT has a large amount of computation and is difficult to implement. With the development of high-speed devices, there are many researches on how to quickly realize long-sequence FFT, and various realization methods have emerged one after another. For example, literature (Ananth Gramam, AnshulGupta, George Karypi s.Introduction to ParallelComputing, SecondEdition[M], Pearson Education, Harlow, England, 2003: 245-250) mentions the use of multiple dedicated chips to form a parallel structure to quickly realize long sequence FFT, but this method is based on a dedicated chip and lacks flexibility. In recent years, FPGA (Field Programm...

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Application Information

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IPC IPC(8): G06F17/14
Inventor 黄正刘亮皋魏席刚周正仙仝芳轩
Owner SHANGHAI BOOM FIBER SENSING TECH
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