Design of excitation synaptic backfield potential (fEPSPs) simulation acquisition front-end system based on FPGA

Abstract

The invention discloses a design and an application method of an excitation synaptic backfield potential (fEPSPs) analog acquisition front-end system based on an FPGA (Field Programmable Gate Array). The system consists of a chopping stable cascode primary amplifier, a gain adjustable secondary amplifier, an AD9226 analog-to-digital conversion circuit, a serial port communication module and necessary peripheral circuits. Wherein the signal conditioning part adopts a two-stage amplification structure; in a signal transmission process, an FIFO (First In First Out) memory is used as a data cache region, a digital FIR (Finite Impulse Response) filter and a zero-phase filtfilt algorithm are fused, and the power consumption and the area are lower while signal two-stage amplification and high-fidelity filtering are performed. The system is based on FPGA control, and the electrophysiological recording analog front end can collect evoked field potential signals.

Description

Technical Field

[0001] The present invention relates to the field of physiological signal detection, and in particular to a design device and an application method of an FPGA-based front-end system for simulating and acquiring excitatory postsynaptic field potentials (fEPSPs). Background Art

[0002] LTP recording and analysis have been widely used to characterize various brain diseases. A large amount of field potential data has been recorded from PD patients and animal models to decode their brain circuits. Currently, there are many large commercial recording devices on the market and they are widely used worldwide. A large number of reports have shown that these electrodes are effective in recording local field potentials and neuronal discharges. Multifunctional in vitro recording devices (such as microelectrode arrays MEA) have become important tools for studying neuronal and synaptic functions. However, there are still many limitations in their practical applications. For example, commercial recording devices have high manufacturing costs; some multi-channel systems are equipped with advanced data analysis software systems, which are more expensive, which undoubtedly greatly increases the cost of research work.

[0003] At the same time, the size and product structure of commercial recording devices are usually fixed and bulky, making it difficult for researchers to customize them according to experimental needs. Microelectrode arrays are usually fixed in configuration, and the position or parameters of a single electrode cannot be individually controlled. This fixed operating mode not only limits the flexibility of experimental design, but also hinders its application in in vivo implantation studies. Therefore, although MEA technology has performed well in in vitro brain slice studies, its high cost, large size, and lack of flexibility have limited its application in a wider range of studies. Summary of the Invention

[0004] In view of the high manufacturing cost and bulky size of commercial recording devices, the present invention aims to provide a miniaturized, low-cost, and highly flexible field potential signal recording device to meet the needs of complex experimental scenarios. The technical solution of the invention is:

[0005] A design of an FPGA-based front-end system for simulating and acquiring excitatory postsynaptic field potentials (fEPSPs) is characterized by the following steps: design of analog front-end circuit performance indicators, design of the analog front-end circuit acquisition part, system performance testing, data preprocessing, and synchronous acquisition of the analog front-end system and MEA.

[0006] (1) Analog front-end circuit performance index design

[0007] The analog front-end system's main control board measures 90mm x 90mm and is capable of continuous 30-40 minute long-term recording of extracellular field potentials. The recorded field potential amplitude deviation is <0.016%, and the frequency drift is <0.023%. The AFE circuit, powered by a 5V battery, isolates the system from AC noise, resulting in an equivalent input noise of <100μVrms. The system utilizes a two-stage amplifier structure consisting of a chopper-stabilized cascode primary amplifier and a gain-adjustable secondary amplifier. The gain can reach 4000-5000x, with the primary amplifier providing 100x and the secondary amplifier 40-50x, enabling high-fidelity amplification of weak signals ranging from 160-360μV. The linearity error of the collected signal is less than 2.5%, with a CMRR at 50Hz exceeding 60dB and a PSRR exceeding 60dB. The gain bandwidth is 1-500Hz, with a low-pass cutoff frequency of <1kHz, and the system's signal-to-noise ratio exceeds 40dB.

[0008] (2) Design of analog front-end circuit acquisition part

[0009] A.FPGA chip

[0010] The FPGA chip serves as the main control unit, responsible for core functions such as clock division, acquisition control, and data caching. The clock division module provides precise timing control for the system, ensuring the synchronization and stability of the sampling process. Regarding data storage and transmission, the main control board uses FIFO memory as a data buffer, effectively resolving the mismatch between data acquisition and transmission rates. The collected data can be transmitted to the host computer in real time via the serial communication module. The transmission protocol uses the standard UART protocol, which offers excellent compatibility and reliability. The host computer parses and visualizes the received data using the serial debugging assistant and MATLAB software, enabling real-time waveform display and dynamic analysis.

[0011] B. Chopper amplifier primary circuit

[0012] This design sets the front-end gain within the range of 40-50dB (100-200 times). The first-stage preamplifier uses a chopper-stabilized common-source common-gate amplifier circuit with a current-balanced architecture. The 1 / f noise and offset voltage can be effectively suppressed through chopping modulation technology. The useful fEPSPs signal is amplified and demodulated back to the baseband. The high-frequency 1 / ff noise and offset components are filtered out through a low-pass filter (LPF). The present invention selects a chopping frequency of 8kHz. This circuit does not contain capacitors, which can eliminate the kT / C noise generated when the capacitor voltage is sampled. The cascode cascade structure formed based on PMOS transistors can reduce the effective noise efficiency factor (NEF). NEF is defined as:

[0013]

[0014] Among them, V rms is the total input referred noise, I tot is the total current, U T is the thermovoltage, k is the Boltzmann constant, T is the absolute temperature, and BW is the -3dB bandwidth of the amplifier. The preamplifier used in the present invention can achieve the primary amplification of the signal while avoiding flicker noise as much as possible. The typical feature of the cascode amplifier circuit is the large voltage gain. The gain calculation formula is:

[0015] |A v |≈g m1 [(g m3 r O3 r O1 )||(g m7 r O7 r O9 )]

[0016] C. Secondary adjustable gain amplifier

[0017] After initial amplification of the tiny signal via a chopper-modulated preamplifier, the present invention employs an AD620 instrumentation amplifier to construct a secondary amplifier circuit for further signal amplification and conditioning. The gain of the second-stage amplifier is configured by a precision resistor RG connected between pins 1 and 8 of the chip. According to the chip manual, the gain factor G = 49.4K / RG + 1. To reduce signal distortion and high-frequency noise interference, the second-stage amplifier maintains a constant gain, resulting in a total gain of 4000-5000x.

[0018] D.12-bit-ADC

[0019] The present invention adopts AD9226, which is a 12-bit resolution, pipeline ADC. The invention adopts a single power supply design. The 12-bit-ADC can provide 2 12 = 4096 quantization levels. With a 5V power supply, the resolution is 5V / 4096 ≈ 1.22mV. The sampling frequency is selected at 20kHz to ensure that at least 100 points are collected within the 5-8ms width of the signal spike, effectively restoring the spike waveform. During continuous sampling, a FIFO buffer is added to the FPGA to temporarily store ADC data before gradually transmitting it via the serial port to avoid sampled data loss.

[0020] (3) System performance test

[0021] The main control board and sampling single-ended microelectrode were designed separately, connected by a double-insulated RF cable. The acquisition control board included a 12-bit ADC, fEPSP recording amplifier, and an FPGA. The single-ended microelectrode (CBARC75) had an impedance of 100-500 kΩ, a rounded tip, and was made of 100 μm tungsten filament. The tube length was 50 mm, and the tip wire length was 10 mm. Stability testing was performed by immersing the single-ended microelectrode and the signal output terminal of a signal generator in distilled water or cerebrospinal fluid. The signal generator output a 100 mV and 200 mV sinusoidal signal, respectively. The output signals of the two control electrodes were monitored in real time using a high-precision oscilloscope. Frequency and dynamic response testing was performed using a signal generator as the signal source. The copper electrode at the output terminal of the signal generator and the recording single-ended microelectrode were simultaneously immersed in cerebrospinal fluid. A sinusoidal signal with a fixed amplitude of 2 mV and a frequency continuously varying from 100 Hz to 500 Hz was applied. The results showed a clear frequency increase. At a gain of 500, when the input signal varied from 2mV to 8mV, the output signal amplitude ranged from 1V to 4V. The results showed that as the input signal amplitude gradually increased, the peak-to-peak value of the output signal collected by the host computer significantly increased, while the waveform remained stable. By varying the input signal amplitude from 160μV to 360μV, the system tested a microvolt-level analog signal. The detected signal gain was approximately 4000 times, with an error of no more than 2.5% from the theoretical gain. These results demonstrate the linear amplification characteristics of the present invention over a wide amplitude range.

[0022] (4) Data preprocessing

[0023] A template matching threshold detection algorithm was used, with a threshold of 0.8, to screen for matching excitatory postsynaptic field potentials (fEPSPs). The segmented signals were preprocessed using a digital FIR filter combined with the filtfilt filter function in the MATLAB toolbox. The design employed a dual approach of battery power and digital FIR filtering to address power line interference. The filtfilt function achieved zero-phase filtering through bidirectional filtering, ensuring consistent amplitude and waveform trends in the filtered fEPSPs.

[0024] (5)Synchronous acquisition of analog front-end system and MEA

[0025] A. Collection, testing, and comparative verification of excitatory postsynaptic potentials (fEPSPs)

[0026] The fEPSPs signals recorded by the two systems were normalized, and the results showed that the difference in normalized amplitude between the AFE and MEA methods for brain slice 1 was 0.8%, and the difference in normalized amplitude between the AFE and MEA methods for brain slice 2 was 4.87%. The difference is less than 5%, which can be considered to be highly consistent in the amplitude range. The correlation coefficient of brain slice 1 is 0.8256, and the correlation coefficient of brain slice 2 is 0.8523. The correlation coefficient in the range of 0.70-0.89 indicates that the two waveforms are highly similar. The normalized mean square error NMSE of the two sets of data for brain slice 1 is 0.0089, and the NMSE of the two sets of data for brain slice 2 is 0.0127. Under general standards, NMSE<0.01 indicates very similar. This illustrates the high reliability of the fEPSPs signal collected by the analog front-end AFE of the present invention.

[0027] B. Long-term potentiation (LTP) acquisition test and comparative verification

[0028] 1. Experimental Procedure: First, continuously acquire basal fEPSPs signals for 10 minutes and record the baseline amplitude. Then, apply high-frequency stimulation for 6 seconds at a frequency of 100 Hz and a current intensity of 60 μA to induce LTP. Finally, continuously record for 20-30 minutes to monitor the maintenance of LTP.

[0029] 2. Results: The amplitude of slice 1 (after approximately 4000x magnification) increased from a baseline of 154mV±3.1mV to 198mV±6.7mV, a 128.57% increase; the amplitude of slice 2 increased from a baseline of 168mV±4.7mV to 211mV±4.6mV, a 125.60% increase; and the amplitude of slice 3 increased from a baseline of 271mV±7.7mV to 327mV±12.1mV, a 120.66% increase. All slices accurately captured changes in fEPSP amplitude and long-term potentiation (LTP) after high-frequency stimulation. A comparison of normalized amplitudes is shown below: The percentage of normalized fEPSP amplitudes before induction in slice 1 was approximately 78%, and after induction it was approximately 100%, with an approximately 1.28-fold increase after HFS. In slice 2, the percentage of normalized fEPSP amplitudes before induction was approximately 125%, and after induction it was approximately 155%, with an approximately 1.25-fold increase after HFS. Data from the same slice were processed based on baseline normalization. During the first ten minutes of HFS, baseline fluctuations remained within the range of 0.95-1.05, with a standard deviation of less than 5.36%. During the high-frequency stimulation phase of HFS, amplitudes increased significantly. For approximately 15-20 minutes after the end of stimulation, fEPSP amplitudes remained stable between 1.05-1.25, with a standard deviation of less than 8.78%. Compared to MEA acquisition results, the AFE analog front-end recordings exhibited an error of <3.57%, a normalized amplitude variance of <5%, a correlation coefficient of <0.85, and a normalized mean square error (NMSE) of <0.013.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] A. The present invention is a miniaturized, low-power electrophysiological recording system based on a field-programmable gate array (FPGA). The size of the main control board is controlled within 9cm×9cm, and it integrates chopping amplifier, gain adjustment, analog-to-digital conversion, and data transmission modules. Clock synchronization, data caching, and real-time processing are achieved through FPGA, significantly improving the flexibility and scalability of the system. Compared with traditional large-scale commercial equipment, the present invention maintains the same signal quality (gain of 72-74dB in the 1-300Hz frequency band, gain error <2.5%) while reducing the volume by 80%, reducing the cost by 90%, and reducing the power consumption to the milliwatt level. It is also more compact and flexible, suitable for complex experimental scenarios.

[0032] B. A chopper-stabilized cascode amplifier circuit, combined with a current-balanced architecture, suppresses low-frequency 1 / f noise and offset voltage through an 8kHz chopping frequency. The secondary amplifier uses an AD620 instrumentation amplifier, which achieves dynamic gain adjustment (total gain 4000-5000x) through digital control. It supports high-fidelity amplification of microvolt-level signals (160-360μV) with a linearity error of no more than 2.5%.

[0033] C. A hybrid anti-interference solution combining 5V battery power supply with digital FIR filters and the filtfilt filter function in the MATLAB toolbox is proposed to effectively suppress 50Hz power frequency noise. An adaptive FIR filter is implemented through FPGA parallel computing, retaining the effective frequency band of 1-300Hz and filtering out high-frequency artifacts and baseline drift. Combined with the zero-phase filtfilt filtering algorithm, phase distortion is eliminated to ensure signal waveform integrity. Compared with traditional analog notch filters, the analog front-end acquisition method proposed in this invention can more effectively avoid useful signal loss by achieving zero-phase filtering through bidirectional filtering. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is the overall flow chart of the present invention;

[0035] Figure 2 This is the trend diagram of the signal waveform collected by this device and MEA after normalization of different brain slices;

[0036] Figure 3 It is a graph showing the waveform and amplitude changes of fEPSPs in multiple groups at baseline and after HFS high-frequency stimulation;

[0037] a. fEPSP amplitudes of multiple brain slice data recorded by MEA;

[0038] b. Amplitude of brain slice data recorded by AFE;

[0039] c. Amplitude of the second brain slice data recorded by AFE;

[0040] d. Amplitude of three data of brain slice recorded by AFE;

[0041] Figure 4 It is the comparison of the normalized amplitudes of the signals before and after HFS collected by the analog front-end circuit;

[0042] a. Brain slice image comparison;

[0043] b. Comparison of two amplitudes in brain slices;

[0044] Figure 5 It is a normalized long-term potentiation (LTP) comparison map collected in parallel from a group of brain slices; DETAILED DESCRIPTION

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0046] Implementation method one:

[0047] Step 1: Design and build the structure of the FPGA-based front-end system for simulating the acquisition of excitatory postsynaptic field potentials (fEPSPs). This system mainly includes the FPGA chip circuit, a capacitor-less chopper preamplifier with a current-balanced architecture, a gain-adjustable secondary amplifier, an AD9226 analog-to-digital conversion circuit, and a serial communication circuit. The software functions of the phase-locked loop (PLL), data buffer (FIFO), ADC data processing, and serial transmission are implemented in the FPGA chip.

[0048] Step 2: Determine various parameters such as sampling frequency based on the performance indicators to be achieved;

[0049] Step 3: Testing the acquisition main control board module and the acquisition single-ended microelectrode system, including stability, frequency and dynamic response, and overall testing of the microvolt-level analog signal system. The input signal amplitude ranges from 160μV to 360μV, and the detected signal gain is about 4000 times, with an error of no more than 2.5% from the theoretical gain.

[0050] Step 4: The AFE and MEA recorded signals in parallel and compared them, including the acquisition, testing and comparison of excitatory postsynaptic potentials (fEPSPs) and long-term potentiation (LTP). The waveform similarity was quantified using normalized amplitude, correlation coefficient, and mean square error with a commercial multi-electrode array MEA, demonstrating the real-time monitoring capability and effectiveness of the AFE.

Claims

1. Design of an FPGA-based front-end system for simulating and acquiring excitatory postsynaptic field potentials (fEPSPs), characterized by: The system includes analog acquisition front-end (AFE) functional parameter design, AFE circuit performance design, AFE system performance test and AFE experimental verification. The detailed process is as follows: The first step is to design the AFE functional parameters: the analog front-end system main control board is 90mm×90mm in size and is capable of recording extracellular field potentials for 30-40 minutes. The recorded field potential amplitude deviation is less than 0.016%, and the frequency drift is less than 0.023%. At a sampling frequency of 20kHz, it can accurately capture weak signals of 160-360μV, achieve a gain of 72-74dB in the 1-300Hz frequency band, and a gain error of less than 2.5%. The second step is to design the performance of the analog front-end (AFE) circuit: the analog front-end (AFE) circuit is powered by a 5V battery to isolate AC noise, with an equivalent input noise of <100μVrms. It uses a chopper-stabilized cascode primary amplifier and a gain-adjustable secondary amplifier to form a two-stage amplification structure. The gain can reach 4000-5000 times, of which the primary amplifier can amplify 100 times and the secondary amplifier can amplify 40-50 times, meeting the high-fidelity amplification requirements of weak-level signals of 160-360μV. Step 3: AFE system performance test: Using a single-ended microelectrode CBARC75 with an impedance of 100-500kΩ, a circular tip, a 10mm filament length, 100μm tungsten wire, and a tube length of 50mm, the system demonstrated a signal gain of 4000-5000 times, with a linear error of no more than 2.5%, a CMRR@50Hz>60dB, a PSRR>60dB, a gain bandwidth of 1-500Hz, a low-pass cutoff frequency<1kHz, and a system signal-to-noise ratio greater than 40dB. The fourth step is the AFE experimental verification: a threshold detection algorithm based on the template matching method is used, with the threshold set to 0.8, to screen out matching excitatory postsynaptic field potentials (fEPSPs) signals. A digital FIR filter combined with the filtfilt filter function is used to preprocess the signals, eliminating phase distortion while retaining the 1-300 Hz effective signal. The fEPSPs signals collected by the AFE analog front end and the multi-electrode array (MEA) are recorded in parallel. Compared with the MEA acquisition results, the AFE analog front end recording results have an error of <3.57%, a normalized amplitude difference of <5%, a correlation coefficient of <0.85, and a normalized mean square error (NMSE) of <0.

013.

2. The method according to claim 1, characterized in that The overall structure mainly includes FPGA chip circuit, capacitor-free chopper preamplifier with current balance architecture, gain-adjustable secondary amplifier, AD9226 analog-to-digital conversion circuit and serial communication circuit; among them, the software functions of phase-locked loop (PLL), data buffer (FIFO), ADC data processing and serial transmission are implemented in the FPGA chip.

3. The method according to claim 1, characterized in that The acquisition method is to continuously collect basal fEPSPs signals for 10 minutes and record the baseline amplitude. Subsequently, high-frequency stimulation HFS with a duration of 6 seconds, a frequency of 100 Hz, and a current intensity of 60 μA is applied to induce LTP, and the dynamic changes of postsynaptic currents are captured in real time. Finally, the recording is continued for 20-30 minutes to record the maintenance of LTP, and the data are collected and compared synchronously with MEA.

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