Apparatus and method for performing sensing operations

Abstract

This application is directed to techniques for performing sensing operations. In some examples, a memory device can include a pair of transistors to pre-charge a digit line. A first transistor of the pair of transistors can be coupled with a first node, and a second transistor of the pair of transistors can be coupled with a second node. In some cases, the first node and the second node can be selectively coupled via a transistor. The first transistor and the second transistor can be activated to pre-charge the first node and the second node. In some examples, a pulse can be applied to a capacitor coupled with the second node to transfer charge to the digit line. In some cases, a common-source common-gate transistor can maintain or control a voltage of the digit line to be at or below an upper operating voltage of the memory cell.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 646,259, filed December 28, 2021, entitled “Technologies to Perform a Sensing Operation”, which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to technologies for performing sensing operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write states into the memory device or program states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can be non-volatile because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] A method is described. The method may include: during a first phase of an access operation of a memory cell, pre-charging a first node and a second node to a first voltage, the first node being coupled to the second node via a transistor; during a second phase of the access operation, coupling a storage element of the memory cell to the first node, wherein the storage element is configured to transfer a first charge from the first node at least partially based on the coupling of the storage element to the first node during the second phase of the access operation; during a third phase of the access operation, transferring a second charge to the second node, wherein the transistor transfers a third charge to the first node at least partially based on the transfer of the second charge to the second node; and during a fourth phase of the access operation, transferring a fourth charge from the second node, wherein a second voltage of the first node is at least partially based on a fifth charge transferred from the first node at least partially based on the coupling of the storage element to the first node during at least one of the third or fourth phases.

[0007] Describe a device. The device may include: a first switching assembly coupled to a first node and configured to precharge the first node to a first voltage during a first phase of an access operation; a transistor having a first terminal coupled to the first node and a second terminal coupled to a second node; a second switching assembly coupled to the second node and configured to precharge the second node to the first voltage during the first phase of an access operation; a memory cell including a storage element and a selection assembly configured to couple the first node to the storage element during a second phase of an access operation, wherein the storage element is configured to transfer a first charge from the first node at least partially based on the coupling of the storage element to the first node during the second phase of the access operation; a capacitor coupled between the second node and a third node; and a pulse generator coupled to the third node and configured to apply a pulse to the third node during a third phase of an access operation, wherein the capacitor is configured to transfer a second charge to the second node at a first transition of the pulse at the third node and transfer a third charge from the second node at a second transition of the pulse at the third node, and wherein a second voltage of the first node is at least partially based on a fourth charge transferred from the first node at least partially based on the storage element during the third phase.

[0008] A device is described. The device may include: a memory cell including a storage element; and a controller coupled to the memory cell and configured such that the device: during a first phase of an access operation of the memory cell, precharges a first node and a second node to a first voltage, the first node being coupled to the second node via a transistor; during a second phase of the access operation, couples the storage element of the memory cell to the first node, wherein the storage element is configured to transfer a first charge from the first node at least partially based on the coupling of the storage element to the first node during the second phase of the access operation; during a third phase of the access operation, transfers a second charge to the second node, wherein the transistor is configured to transfer a third charge to the first node at least partially based on the transfer of the second charge to the second node; and during a fourth phase of the access operation, transfers a fourth charge from the second node, wherein the second voltage of the first node is at least partially based on a fifth charge transferred from the first node at least partially based on the coupling of the storage element to the first node during at least one of the third or fourth phases. Attached Figure Description

[0009] Figure 1 Examples of systems that support the performance of sensing operations based on the examples disclosed herein are shown.

[0010] Figure 2 Examples of memory dies that support the performance of sensing operations according to the examples disclosed herein are shown.

[0011] Figure 3 Examples of circuits supporting techniques for performing sensing operations, based on examples disclosed herein, are shown.

[0012] Figure 4 Examples of timing diagrams illustrating techniques for supporting the execution of sensing operations based on examples disclosed herein are shown.

[0013] Figure 5 A block diagram illustrating a memory device that supports performing sensing operations according to examples disclosed herein.

[0014] Figure 6 The flowchart illustrates one or more methods for performing sensing operations based on examples disclosed herein. Detailed Implementation

[0015] In some cases, memory devices (e.g., FeRAM devices) may implement sensing schemes to determine the logic state stored in the memory cells. For example, a sensing scheme may include pre-charging a digital line coupled to the memory cell. A capacitor (e.g., a ferroelectric capacitor) of the memory cell may then be coupled to the digital line to draw charge from it. In some cases, the amount of charge drawn from the digital line, and therefore the resulting voltage on the digital line, may depend on the logic state stored in the memory cell. In some cases, the sensing scheme may include a boost phase to transfer charge to the digital line as the memory cell draws charge from it. Some sensing schemes may include a longer pre-charging phase to pre-charge the digital line, which can increase system latency and power consumption. Additionally, some sensing schemes may impose undue stress on the memory cell. For example, a large voltage may be applied to the memory cell during the boost phase, which may cause wear or fatigue of the memory cell and potentially reduce its usable lifetime. Therefore, improvements to the sensing methods may be necessary.

[0016] As disclosed herein, a memory device may include circuitry to increase the reliability and efficiency of access operations on memory cells. In some instances, the memory device may include transistors for pre-charging digital lines. For example, a first transistor may be coupled to a first node (e.g., a digital line) and may pre-charge the digital line before selecting a memory cell for a read operation. In some cases, a second transistor may be coupled to a second node, which may have a capacitor used in sensing operations (e.g., sensing or boost capacitors). The second transistor may pre-charge the second node while the digital line is being pre-charged. In some cases, the digital line and the second node may be selectively coupled to each other via transistors (e.g., cascode transistors). During the pre-charging phase of a sensing operation, the first and second transistors may be activated to electrically couple a pre-charging voltage to the first and second nodes, respectively. In some cases, the duration of the pre-charging phase may be relatively short (e.g., compared to a pre-charging operation performed using a single transistor). In some instances, the sensing operation may include a boost phase. During the boost phase, a pulse may be applied to a capacitor coupled to the second node to transfer charge to the digital line. In some cases, a cascode transistor can maintain or control the voltage of the digital line at or below the upper operating voltage of the memory cell, which can alleviate undue stress on the memory cell. Therefore, sensing operations can reduce access operation time, reduce losses on the memory cell, and reduce the voltage used in access operations, which can improve efficiency, improve reliability, and reduce the power consumption of the memory device.

[0017] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figures 3 to 4 The features of this disclosure are described in the context of the circuits and timing diagrams described herein. (This is further elaborated by referring to references.) Figures 5 to 6 The device diagrams and flowcharts describing the techniques for performing sensing operations are provided to further illustrate and further describe these and other features of this disclosure with reference to the device diagrams and flowcharts.

[0018] Figure 1 An example of a system 100 supporting techniques for performing sensing operations according to examples disclosed herein is shown. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0019] System 100 may include electronic device components, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptops, tablets, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0020] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute programs within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other examples. In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0021] Memory device 110 may be a separate device or component operable to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 may be operable to store data of components of host device 105. In some instances, memory device 110 may act as a secondary or subordinate device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0023] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0024] Processor 125 may be operable to provide control or other functions for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0025] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0026] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0027] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as a stack, hierarchy, layer, or die. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two-high stacked memory arrays, three-high stacked memory arrays, four-high stacked memory arrays, five-high stacked memory arrays, six-high stacked memory arrays, seven-high stacked memory arrays, eight-high stacked memory arrays). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share one or more of word lines, digital lines, or board lines.

[0028] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0029] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data in host device 105 or a read command instructing memory device 110 to provide host device 105 with data stored in memory die 160.

[0030] Local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or send data or commands, or both). In some instances, memory device 110 may not include device memory controller 155 and local memory controller 165 or external memory controller 120, which perform the various functions described herein. Thus, local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0031] External memory controller 120 may be operable to enable communication of one or more of the information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret the communication exchanged between components of host device 105 and memory device 110. In some instances, the external memory controller 120, or other components of system 100 or host device 105, or its functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0032] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to serve as part of a channel.

[0033] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or dual data rate (DDR) signaling may be transmitted via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0034] In some instances, memory device 110 or memory array 170 may include circuitry for increasing the reliability and efficiency of access operations to memory cells. In some instances, the circuitry may include a first transistor to precharge a digital line of memory array 170. For example, the first transistor may be coupled to a first node (e.g., a digital line) and may precharge the digital line. A second transistor may be coupled to a second node, which may be coupled to a capacitor (e.g., a sensing capacitor or a boost capacitor). The second transistor may precharge the second node, while the first transistor precharges the digital line. In some cases, the digital line and the second node may be selectively coupled to each other via transistors (e.g., cascode transistors). During the precharge phase of a sensing operation, the first and second transistors may be activated to electrically couple a precharge voltage to the first and second nodes, respectively. In some instances, the sensing operation may include a boost phase. During the boost phase, a pulse may be applied to the capacitor coupled to the second node to transfer charge to the digital line. In some cases, a cascode transistor can maintain or control the voltage of the digital line at or below the upper operating voltage of the memory cell, which can alleviate undue stress on the memory cell.

[0035] Figure 2 An example of a memory die 200 supporting the performance of sensing operations according to examples disclosed herein is shown. The memory die 200 may be used as a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, the memory cells 205 may be arranged in an array, such as referenced in [reference needed]. Figure 1 The memory array 170 is described.

[0036] Memory cell 205 may store states (e.g., polarization states or dielectric charges) representing programmable states in a capacitor. In a FeRAM architecture, memory cell 205 may include capacitor 240, which comprises ferroelectric material to store charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electrical communication between two components.

[0037] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern such as a grid. Access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210, digital lines 215, and / or board lines 220.

[0038] Memory cell 205 can be accessed, for example, by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing word line 210, digital line 215, and board line 220 (e.g., by applying voltage to word line 210, digital line 215, or board line 220). Activating or selecting word line 210, digital line 215, or board line 220 may involve applying voltage to the respective line.

[0039] The access memory unit 205 can be controlled by a row decoder 225, a column decoder 230, and a board driver 235. For example, the row decoder 225 can receive a row address from the local memory controller 265 and activate word line 210 based on the received row address. The column decoder 230 receives a column address from the local memory controller 265 and activates number line 215 based on the received column address. The board driver 235 can receive a board address from the local memory controller 265 and activate board line 220 based on the received board address.

[0040] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to digital line 215.

[0041] Word line 210 may be a conductive line electrically connected to memory cell 205 for performing access operations on memory cell 205. In some architectures, word line 210 may be electrically connected to the gate of switching component 245 of memory cell 205 and may be operable to control the switching component 245 of memory cell 205. In some architectures, word line 210 may be electrically connected to a node of capacitor of memory cell 205, and memory cell 205 may not include a switching component.

[0042] Digital line 215 may be a conductive line connecting memory cell 205 and sensing component 250. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 245 of memory cell 205 may be operable to selectively couple and / or isolate capacitor 240 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may be electrically connected to digital line 215 (e.g., constantly).

[0043] Board line 220 may be a conductive line electrically connected to memory cell 205 for performing access operations on memory cell 205. Board line 220 may be electrically connected to a node (e.g., bottom of cell) of capacitor 240. Board line 220 may cooperate with digital line 215 to bias capacitor 240 during access operations on memory cell 205.

[0044] Sensing component 250 can determine the state (e.g., polarization state or charge) on capacitor 240 stored in memory cell 205, and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output from memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference signal 255 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 250 (e.g., to input / output 260), and can indicate the detected logic state to another component of memory device 110 including memory die 200.

[0045] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 may be used as a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, board driver 235, and sensing components 250 may co-locate with the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0046] The local memory controller 265 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 265 in response to various access commands (e.g., from the host device 105) or otherwise coordinated. The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0047] Local memory controller 265 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of memory die 200. During a read operation, a logical state stored in the memory cells 205 of memory die 200 can be determined. Local memory controller 265 can identify a target memory cell 205 to which a read operation will be performed. Local memory controller 265 can identify a target word line 210, a target digital line 215, and a target board line 220 coupled to the target memory cell 205. Local memory controller 265 can activate the target word line 210, the target digital line 215, and the target board line 220 (e.g., by applying a voltage to the word line 210, the digital line 215, or the board line 220) to access the target memory cell 205. The target memory cell 205 can transfer a signal to sensing component 250 in response to a bias access line. Sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the logic state stored in the memory cell 205.

[0048] In some instances, the memory die 200 may include circuitry for increasing the reliability and efficiency of access operations to the memory cell 205. In some instances, the circuitry may include a first transistor to precharge the digital line 215 of the memory die 200. For example, the first transistor may be coupled to a first node (e.g., digital line 215) and may precharge the digital line 215. A second transistor may be coupled to a second node, which may be coupled to a capacitor (e.g., a sensing capacitor or a boost capacitor). The second transistor may precharge the second node, while the first transistor precharges the digital line 215. In some cases, the digital line 215 and the second node may be selectively coupled to each other via transistors (e.g., cascode transistors). During the precharge phase of a sensing operation, the first and second transistors may be activated to electrically couple a precharge voltage to the first and second nodes, respectively. In some instances, the sensing operation may include a boost phase. During the boost phase, a pulse may be applied to the capacitor coupled to the second node to transfer charge to the digital line. In some cases, the cascode transistor can maintain or control the voltage of the digital line at or below the upper operating voltage of the memory cell 205, which can alleviate undue stress on the memory cell 205.

[0049] Figure 3 An example of circuit 300 supporting the performance of sensing operations according to examples disclosed herein is shown. Circuit 300 may include and may be as referenced Figure 2The memory cell 305 and the digital line 315 (e.g., the first node) coupled to the sensing component 350 are examples of the corresponding components described. For example, the memory cell may include a selector component, such as a transistor 306 having a gate coupled to a word line 308, to selectively couple storage elements of the memory cell, such as a ferroelectric capacitor 307, wherein the digital line 315 has an intrinsic capacitance represented by the capacitor 355.

[0050] In some cases, the charge stored by the ferroelectric capacitor 307 may include a polarization or dipole moment associated with the charge. For example, the ferroelectric capacitor 307 may store a first dipole moment associated with a first logic state, or a second dipole moment associated with a second logic state (e.g., opposite to the first dipole moment). In some cases, if the memory cell stores a first state and a voltage greater than the lower operating voltage is applied to the ferroelectric capacitor, the dipole in the memory cell may switch (e.g., from a first direction to a second direction) and thus draw or transfer charge from the digital line 315, thereby reducing the voltage of the digital line 315. Alternatively, if the memory cell stores a second state, applying a voltage greater than the lower operating voltage may not switch the dipole (e.g., because the dipole may already be pointing in the second direction). Therefore, the ferroelectric capacitor 307 may draw a reduced charge from the digital line 315 (e.g., relative to the charge drawn from the switched dipole). In some cases, applying a voltage greater than the upper operating voltage of the memory cell 305 may damage or wear down the ferroelectric capacitor. Therefore, during sensing operations, a voltage greater than the lower operating voltage of memory cell 305 but less than the upper operating voltage of memory cell 305 may be required.

[0051] In some cases, circuit 300 may include capacitor 320 to transfer charge to digital line 315, for example, via transistor 310 during sensing operation. Transistor 310 may be, for example, an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) or an n-MOS transistor. An n-MOS transistor may include a gate, a source terminal, and a drain terminal. If the voltage on the gate is higher than the threshold voltage at the source or drain terminal, the n-MOS transistor may couple the drain terminal to the source terminal. If the voltage on the gate is not higher than the threshold voltage at the source or drain terminal, the n-MOS transistor may insulate the source terminal from the drain terminal (e.g., in the cutoff or subthreshold region). As used herein, transistor terminals may refer to interchangeable source or drain terminals. In some instances, the first plate of capacitor 320 may be coupled to the terminals of transistor 310 via a second node 325. During sensing operation, a signal or voltage pulse may be applied to the second plate 340 of capacitor 320 to transfer charge to the second node 325. In some instances, circuit 300 may include a pulse generator or other circuitry to apply voltage pulses to the terminals of capacitor 320. The charge or a portion of the charge stored in capacitor 320 may then be transferred to digital line 315, for example, via second node 325 and transistor 310. In some cases, transferring charge to digital line 315 during sensing operation may be facilitated, for example, by maintaining the voltage of digital line 315 above the lower operating voltage, thereby aiding in switching the dipoles of the ferroelectric capacitor.

[0052] Circuit 300 may include a pair of switching components, such as switching component 330 and switching component 335. In some cases, switching component 330 and switching component 335 may each be an instance of a transistor, such as a p-type MOSFET or a p-mos transistor. A p-mos transistor may include a gate, a source terminal, and a drain terminal. If the voltage on the gate is lower than the source or drain terminal by a voltage difference exceeding a threshold voltage, then the p-mos transistor couples the drain terminal to the source terminal. If the voltage on the gate is not lower than the source or drain terminal by a voltage difference exceeding a threshold voltage (e.g., in the cutoff or subthreshold region), then the p-mos transistor insulates the source terminal from the drain terminal. Therefore, if a high voltage (e.g., a voltage higher than the threshold voltage of the switching component that is lower than the voltage on the terminal of the switching component) is applied to the gate of the switching component 330 or the switching component 335, then the switching component 330 and the switching component 335 can be deactivated (e.g., become insulated), and if a low voltage is applied to the gate of the switching component 330 or the switching component 335 (e.g., the voltage on the terminal of the switching component is higher than the threshold voltage of the switching component than the gate of the switching component), then the switching component 330 and the switching component 335 can be activated (e.g., become conductive).

[0053] In some cases, switching components 330 and 335 may be configured to precharge digital line 315 and second node 325 to a first voltage (e.g., a precharge voltage). For example, switching components 330 and 335 may, when activated, couple digital line 315 and second node 325 to power node 332 at the first voltage. For example, switching components 330 and 335 may be activated during a precharge phase (e.g., electrically couple digital line 315 and second node 325 to the power node) to bias digital line 315 and second node 325 with the first voltage. In some cases, switching components 330 and 335 may be deactivated after biasing digital line 315 and second node 325. Therefore, digital line 315 and second node 325 may float at the first voltage. In some cases, the first voltage may be equal to or substantially equal to the upper operating voltage of memory cell 305. Alternatively, a single switching component (e.g., switching component 330 or switching component 335) may be used to precharge digital line 315 or second node 325. In such cases, transistor 310 may be configured to precharge the other node. That is, if switching component 330 is used to charge digital line 315, then the second node may be precharged via transistor 310, and if switching component 335 is used to precharge second node 325, then the digital line may be precharged via transistor 310.

[0054] Transistor 310 may be an example of a cascode transistor and can therefore be configured to maintain the voltage of digital line 315 at or below a first voltage (e.g., the upper operating voltage of memory cell 305). In some cases, transistor 310 may be an example of an n-type MOSFET or an n-MOS. That is, if a high voltage is applied to the gate of transistor 310 (e.g., the gate-to-source voltage becomes higher than the threshold voltage of transistor 310), then transistor 310 can be activated, and if a low voltage is applied to the gate of transistor 310 (e.g., the gate-to-source voltage becomes lower than the threshold voltage of transistor 310), then transistor 310 can be deactivated. To maintain the voltage of digital line 315, the gate of transistor 310 may be biased to a voltage higher than the first voltage, for example, a voltage approximately equal to the sum of the first voltage and the threshold voltage of transistor 310. Therefore, transistor 310 may not transfer voltages substantially higher than the first voltage to digital line 315. In some cases, a gate bias may be applied to transistor 310 to control the voltage transferred via transistor 310.

[0055] Figure 4 An example of timing diagram 400 supporting the performance of sensing operations according to examples disclosed herein is shown. In some cases, timing diagram 400 may be implemented by circuitry included in a memory device or memory system, such as as referenced herein. Figure 3The circuit 300 is described. Timing diagram 400 may show the voltage 410 of one or more components or nodes of the circuit over a period of time 405, such as a first node 415 coupled to a memory cell for memory cell access operations (e.g., a digital line, as shown in reference). Figure 3 The voltage of the described digital line 315) and the second node 420 coupled to the first node (e.g., as referenced) Figure 3 The voltage of the second node (325) described. Alternatively, the circuit may include a common-source cascode transistor positioned between the first and second nodes, such as as referenced. Figure 3 The transistor 310 is described.

[0056] In some cases, timing diagram 400 may include a precharge signal 425. The precharge signal 425 may be applied to activate one or more switching components of the circuit, as shown in reference [reference needed]. Figure 3 The described switching components 330 and 335. Additionally, timing diagram 400 may include a boost pulse 430. The boost pulse 430 may be applied to a capacitor in the circuit, such as as referenced. Figure 3 The capacitor 320 is described and can be configured to transfer charge to a second node (e.g., to increase or boost the voltage of the second node 420).

[0057] In some instances, the timing diagram may include a first phase 435, which may be an example of a pre-charge phase. During the first phase 435, the pre-charge signal 425 may be switched. For example, the pre-charge signal 425 may transition from a high voltage to a low voltage. In some cases, transitioning the pre-charge signal 425 to a low voltage activates a switching component of the circuit (e.g., if the switching component is a p-MOS transistor), and may electrically couple a first node, a second node, or both to a first voltage 440, which may be an example of a pre-charge voltage. The first voltage 440 may be higher than the lower operating voltage of the memory cell (e.g., high enough to switch the dipole of the memory cell) and lower than or equal to the upper operating voltage of the memory cell.

[0058] Therefore, the switching assembly can bias the first node and the second node to the first voltage 440. In some cases, the capacitor can also be biased to the first voltage 440 (e.g., because the second terminal of the capacitor can be at ground voltage). Alternatively or additionally, during the first phase 435, the gate of the cascode transistor can be biased to a second voltage, for example, a voltage equal to the sum of the first voltage 440 and the threshold voltage of the cascode transistor.

[0059] In some cases, the first stage 435 may involve transitioning the precharge signal 425 from a low voltage to a high voltage to deactivate the switching components. Therefore, the first node and the second node may be isolated from the first voltage 440 (e.g., electrically isolated). Thus, the first node and the second node may be in a floating state. In some cases, the duration of the first stage 435 may be relatively fast (e.g., about five nanoseconds (ns)). For example, since the circuit may include multiple switching components (e.g., two switching components), the duration of the first stage 435 may be shorter than that of a circuit containing a single switching component to perform the precharge operation.

[0060] In some cases, timing diagram 400 may include a second phase 445, which may be an example of a signal generation phase. During the second phase 445, the voltage of word line 450 may increase, which may couple the memory cell to the first node (e.g., by activating a transistor positioned between the memory cell and the first node). Therefore, the voltage of the first node 415 may begin to decrease. In some cases, the memory cell may store a first state (e.g., logic "1") and may draw a first charge from the first node. Alternatively, the memory cell may store a second state (e.g., logic "0") and may draw a second charge greater than the first charge. For example, if the memory cell stores a second state, then the voltage of the first node 415 may be large enough to switch all or part of the dipole of the memory cell. In some instances, the amount of charge drawn from the first node may depend on the capacitance of the first node (e.g., intrinsic capacitance), which may be determined in part by the length or size of the first node. For example, the first node may be large enough to draw all the charge stored in the memory cell. Alternatively, when the digital line is precharged to a voltage no greater than the operating voltage of the memory cell, the digital line may not be large enough to extract all the charge stored in the memory cell, and alternatively, a portion of the charge stored in the memory cell may be extracted.

[0061] Therefore, the voltage of the first node 415 can depend on the state of the memory cell. For example, if the memory cell stores a first state, the voltage of the first node 415 can drop to a first value 460-a, and if the memory cell stores a second state, the voltage of the first node 415 can drop to a second value 460-b. In some cases, during the second phase 445, the first node can draw charge from the second node, which can reduce the voltage of the second node 420. For example, if the memory cell stores a first state, the voltage of the second node 420 can drop to a first value 465-a. Alternatively, if the memory cell stores a second state, the voltage of the second node 420 can drop to a second value 465-b.

[0062] In some instances, timing diagram 400 may include a third stage 470, which may be an example of a boost stage that provides additional charge to the memory cell. During the third stage 470, a boost pulse 430 may be applied to a capacitor to transfer charge to a second node. For example, boost pulse 430 may apply a voltage to the plates of a capacitor, which may then transfer charge to the second node. Thus, the voltage at the second node 420 may, for example, be increased to a voltage higher than a first voltage (e.g., higher than a pre-charge voltage). In some instances, the second stage 445 and the third stage 470 may at least partially overlap in time. For example, boost pulse 430 may be applied to the capacitor when the memory cell draws charge from the first node.

[0063] The cascode transistor can be activated during the third phase 470, the second phase 445, or both. Therefore, the first node can be coupled (e.g., electrically coupled) to the second node during at least a portion of the third phase 470, and charge can be transferred from the second node to the first node. In some cases, the voltage of the second node 420 can be boosted to a voltage higher than the upper operating voltage of the memory cell. Therefore, the cascode transistor can be configured to maintain or control the voltage of the first node 415 at or below the upper operating voltage of the memory cell. For example, the gate of the cascode transistor can be biased to a voltage approximately equal to the sum of the first voltage 440 and the threshold voltage of the cascode transistor. In some cases, a second pulse or a second boost pulse can be applied to the capacitor. For example, the boost pulse 430 can include an additional pulse that can transfer additional charge to the second node.

[0064] In some cases, timing diagram 400 may include a fourth phase 475. During the fourth phase 475, boost pulse 430 may terminate (e.g., the voltage applied to the capacitor may transition from a high voltage to a low voltage). In some cases, the memory cell may continue to draw charge from the first node. Therefore, the voltage at the first node 415 and the voltage at the second node 420 may decrease.

[0065] In some cases, during the third phase 470, and if the memory cell stores a second state, the boost pulse 430 may cause one or more dipoles of the memory cell to switch, for example, if all dipoles of the memory are not switched during the second phase 445. Therefore, the memory cell may draw additional charge from the first node during the fourth phase 475. Consequently, the voltage of the first node 415 and the voltage of the second node 420 may, for example, decrease to a voltage lower than the voltage reached during the second phase 445. Alternatively or (e.g., if the memory cell stores a first value), the dipoles may not switch during the boost pulse 430. Therefore, after the third phase 470, the voltage of the first node 415 may return to the same or substantially the same voltage reached during the second phase 445.

[0066] The final voltage at the first node 415 (e.g., the voltage after the fourth stage 475) can therefore depend on the state stored in the memory cell. Thus, in some cases, the sensing component (e.g., as a reference) Figure 3 The described sensing component 350 can be used to determine the state of a memory cell. For example, the sensing component may include a sensing amplifier to compare the voltage of the first node 415 with a reference voltage to determine whether the memory cell stores a first state or a second state. For example, the reference voltage may be between the voltage levels of the first node 415 after the first state and the second state after the fourth stage 475. In some instances, after the sensing component has determined the state of the memory cell, the circuitry may perform an operation to restore or write the sensed state back to the memory cell, such as a refresh operation.

[0067] Figure 5 A block diagram 500 illustrates a memory device 520 that supports performing sensing operations according to examples disclosed herein. The memory device 520 may be used as a reference. Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of components for performing various aspects of the techniques for performing sensing operations as described herein. For example, memory device 520 may include a precharge component 525, a selector component 530, a charge transfer component 535, a voltage control component 540, a pulse component 545, a logic state component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0068] Precharge component 525 may be configured or otherwise support means for precharging a first node and a second node to a first voltage during a first phase of access operation of a memory cell, the first node being coupled to the second node via a transistor. Selector component 530 may be configured or otherwise support means for coupling a memory element of a memory cell to the first node during a second phase of access operation, wherein the memory element is configured to transfer a first charge from the first node at least partially based on coupling the memory element to the first node during the second phase of access operation. Charge transfer component 535 may be configured or otherwise support means for transferring a second charge to the second node during a third phase of access operation, wherein the transistor transfers a third charge to the first node at least partially based on transferring the second charge to the second node. In some instances, charge transfer component 535 may be configured or otherwise support means for transferring a fourth charge from the second node during a fourth phase of access operation, wherein the second voltage of the first node is at least partially based on a fifth charge transferred from the first node at least partially based on coupling the memory element to the first node during at least one of the third or fourth phases.

[0069] In some instances, voltage control component 540 may be configured or otherwise support means for applying a third voltage to the gate of a transistor such that the transistor transmits a fourth voltage, not higher than the first voltage, from the second node to the first node during the third phase.

[0070] In some instances, the magnitude of the third voltage is greater than the magnitude of the first voltage.

[0071] In some instances, during the fourth phase, the transistor transfers at least a portion of the fourth charge from the first node to the second node based at least in part on the application of a third voltage to the transistor's gate.

[0072] In some instances, the pulse component 545 may be configured or otherwise support means for applying a pulse to a third node coupled to the second node via a capacitor during the third phase of an access operation, wherein the transfer of a second charge to the second node is based at least in part on the application of the pulse.

[0073] In some instances, the first terminal of the transistor is coupled to the second node, and the second terminal of the transistor is coupled to the first node.

[0074] In some instances, the pre-charge component 525 may be configured or otherwise support means for activating a first switching component coupled to a first node, wherein pre-charging the first node to a first voltage is at least partially based on activating the first switching component. In some instances, the pre-charge component 525 may be configured or otherwise support means for activating a second switching component coupled to a second node, wherein pre-charging the second node to a first voltage is at least partially based on activating the second switching component.

[0075] In some instances, the precharge component 525 may be configured or otherwise support a component for deactivating the first switching component. In some instances, the precharge component 525 may be configured or otherwise support a component for deactivating the second switching component, wherein coupling the storage element to the first node is based at least in part on deactivating the first switching component and deactivating the second switching component.

[0076] In some instances, the first switching component, the second switching component, or both contain p-mos transistors.

[0077] In some instances, the logic state component 550 may be configured or otherwise support means for determining the logic state of a memory cell based at least in part on the transfer of a fourth charge, wherein the logic state of the memory cell is based at least in part on the second voltage of the first node.

[0078] In some instances, the second and third phases overlap at least partially in time.

[0079] In some instances, the magnitude of the first charge is based at least in part on the logical state of the memory cell.

[0080] In some instances, memory cells contain ferroelectric capacitors.

[0081] Figure 6 The flowchart illustrates a method 600 that supports performing sensing operations according to examples disclosed herein. Operation of method 600 may be implemented by a memory device or its components as described herein. For example, operation of method 600 may be performed by... (See reference...) Figures 1 to 5 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0082] At 605, the method may include pre-charging a first node and a second node to a first voltage during a first phase of an access operation of a memory cell, the first node being coupled to the second node via a transistor. The operation at 605 may be performed according to examples disclosed herein. In some examples, it may be performed via, as referenced... Figure 5The precharge component 525 described performs the operation of 605.

[0083] At 610, the method may include coupling a storage element of a memory cell to a first node during a second phase of the access operation, wherein the storage element is configured to transfer a first charge from the first node at least in part based on coupling the storage element to the first node during the second phase of the access operation. The operation of 610 may be performed according to examples disclosed herein. In some examples, it may be performed via, as referenced... Figure 5 The selector component 530 described performs the operation of 610.

[0084] At 615, the method may include transferring a second charge to a second node during the third phase of the access operation, wherein the transistor transfers a third charge to the first node based at least in part on the transfer of the second charge to the second node. The operation at 615 may be performed according to examples disclosed herein. In some instances, it may be performed via, as referenced... Figure 5 The described charge transfer component 535 performs the operation of 615.

[0085] At 620, the method may include transferring a fourth charge from the second node during a fourth phase of the access operation, wherein the second voltage of the first node is based at least in part on a fifth charge transferred from the first node during at least one of the third or fourth phases, based at least in part on the coupling of the storage element with the first node. The operation at 620 may be performed according to examples disclosed herein. In some examples, it may be performed via, as referenced... Figure 5 The described charge transfer component 535 performs the operation of 620.

[0086] In some instances, the apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing processor-executable instructions) or any combination thereof for performing aspects of this disclosure:

[0087] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising, or any combination thereof, features, circuitry, logic, components, or instructions for: pre-charging a first node and a second node to a first voltage during a first phase of an access operation of a memory cell, the first node being coupled to the second node via a transistor; coupling a storage element of the memory cell to the first node during a second phase of the access operation, wherein the storage element is configured to transfer a first charge from the first node at least partially based on the coupling of the storage element to the first node during the second phase of the access operation; transferring a second charge to the second node during a third phase of the access operation, wherein the transistor transfers a third charge to the first node at least partially based on the transfer of the second charge to the second node; and transferring a fourth charge from the second node during a fourth phase of the access operation, wherein a second voltage of the first node is at least partially based on a fifth charge transferred from the first node at least partially based on the coupling of the storage element to the first node during at least one of the third or fourth phases.

[0088] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to aspect 1 further includes an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for applying a third voltage to the gate of a transistor such that the transistor transmits a fourth voltage, not higher than the first voltage, from the second node to the first node during a third phase.

[0089] Aspect 3: The method, apparatus or non-transitory computer-readable medium according to aspect 2 further includes features, circuit systems, logic, components or instructions, or any combination thereof, for operation in which the magnitude of the third voltage is greater than the magnitude of the first voltage.

[0090] Aspect 4: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 2 to 3 further comprises features, circuitry, logic, components or instructions, or any combination thereof, for the following operation: during the fourth phase, the transistor transfers at least a portion of the fourth charge from the first node to the second node based at least in part on the application of a third voltage to the gate of the transistor.

[0091] Aspect 5: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 4 further comprises features, circuitry, logic, components or instructions, or any combination thereof, for the operation of applying a pulse to a third node coupled to the second node via a capacitor during a third phase of an access operation, wherein the transfer of a second charge to the second node is based at least in part on the application of the pulse.

[0092] Aspect 6: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 5 further includes features, circuit systems, logic, components or instructions, or any combination thereof, for operation of: a first terminal of a transistor coupled to a second node, and a second terminal of a transistor coupled to a first node.

[0093] Aspect 7: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 6 further comprises features, circuitry, logic, components, or instructions, or any combination thereof, for: activating a first switching assembly coupled to a first node, wherein precharging the first node to a first voltage is at least partially based on activating the first switching assembly; and activating a second switching assembly coupled to a second node, wherein precharging the second node to the first voltage is at least partially based on activating the second switching assembly.

[0094] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to aspect 7 further includes features, circuitry, logic, components, or instructions, or any combination thereof, for: deactivating a first switching component; and deactivating a second switching component, wherein coupling the storage element to the first node is based at least in part on deactivating the first switching component and deactivating the second switching component.

[0095] Aspect 9: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 7 to 8 further includes features, circuitry, logic, components or instructions for operation, or any combination thereof: a first switching assembly, a second switching assembly or both of which include p-mos transistors.

[0096] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 9 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for determining the logical state of a memory cell based at least in part on the transfer of a fourth charge, wherein the logical state of the memory cell is based at least in part on the second voltage of the first node.

[0097] Aspect 11: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 10 further includes features, circuit systems, logic, components or instructions, or any combination thereof, for operations in which the second and third phases at least partially overlap in time.

[0098] Aspect 12: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 11 further includes an operation, feature, circuit system, logic, component or instruction, or any combination thereof, for the following: the magnitude of the first charge is based at least in part on the logical state of the memory cell.

[0099] Aspect 13: The method, apparatus or non-transitory computer-readable medium according to any one of aspects 1 to 12 further includes features, circuit systems, logic, components or instructions, or any combination thereof, for the following operations: memory cells include ferroelectric capacitors.

[0100] It should be noted that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0101] Describe a device. An overview of aspects of the device as described herein is provided below:

[0102] Aspect 14: An apparatus comprising: a first switching assembly coupled to a first node and configured to precharge the first node to a first voltage during a first phase of an access operation; a transistor having a first terminal coupled to the first node and a second terminal coupled to a second node; a second switching assembly coupled to a second node and configured to precharge the second node to the first voltage during the first phase of an access operation; and a memory cell comprising a storage element and a selection assembly configured to couple the first node to the storage element during a second phase of an access operation, wherein the storage element is configured to be at least partially based on the access... During the second phase of operation, a storage element is coupled to a first node to transfer a first charge from the first node; a capacitor is coupled between the second and third nodes; and a pulse generator is coupled to the third node and configured to apply a pulse to the third node during the third phase of the access operation, wherein the capacitor is configured to transfer a second charge to the second node at a first transition of the pulse at the third node and to transfer a third charge from the second node at a second transition of the pulse at the third node, and wherein the second voltage of the first node is at least partially based on a fourth charge transferred from the first node during the third phase, at least partially based on the storage element.

[0103] Aspect 15: The apparatus according to aspect 14, wherein during the third phase of the access operation, the gate voltage of the transistor is biased to a third voltage greater than the first voltage.

[0104] Aspect 16: The device according to any one of aspects 14 to 15, wherein the first switching component and the second switching component are activated at least in part based on an activation signal during the first phase, and the coupling of the first node to the storage element is based at least in part on deactivating the first switching component and deactivating the second switching component.

[0105] Aspect 17: The device according to any one of aspects 14 to 16 further includes: a sensing circuit configured to determine the logic state of a memory cell based at least in part on a second voltage of the first node.

[0106] Describe a device. An overview of aspects of the device as described herein is provided below:

[0107] Aspect 18: An apparatus comprising: a memory cell including a storage element; and a controller coupled to the memory cell and configured such that the apparatus: during a first phase of an access operation of the memory cell, precharges a first node and a second node to a first voltage, the first node being coupled to the second node via a transistor; during a second phase of the access operation, couples the storage element of the memory cell to the first node, wherein the storage element is configured to transfer a first charge from the first node at least partially based on the coupling of the storage element to the first node during the second phase of the access operation; during a third phase of the access operation, transfers a second charge to the second node, wherein the transistor is configured to transfer a third charge to the first node at least partially based on the transfer of the second charge to the second node; and during a fourth phase of the access operation, transfers a fourth charge from the second node, wherein the second voltage of the first node is at least partially based on a fifth charge transferred from the first node at least partially based on the coupling of the storage element to the first node during at least one of the third or fourth phases.

[0108] Aspect 19: The device according to aspect 18, wherein the controller is further configured such that the device: applies a third voltage to the gate of a transistor such that the transistor transmits a fourth voltage, not higher than the first voltage, from the second node to the first node during the third phase.

[0109] Aspect 20: The device according to aspect 19, wherein the magnitude of the third voltage is greater than the magnitude of the first voltage.

[0110] Aspect 21: The apparatus according to any one of aspects 18 to 20, wherein a first terminal of the transistor is coupled to a second node, and a second terminal of the transistor is coupled to a first node.

[0111] Aspect 22: The device according to any one of aspects 18 to 21, wherein the controller is further configured such that the device: activates a first switching component coupled to a first node, wherein precharging the first node to a first voltage is at least partially based on activating the first switching component; and activates a second switching component coupled to a second node, wherein precharging the second node to a first voltage is at least partially based on activating the second switching component.

[0112] Aspect 23: The device according to aspect 22, wherein the controller is further configured to cause the device to: deactivate the first switching component; and deactivate the second switching component, wherein coupling the storage element to the first node is based at least in part on deactivating the first switching component and deactivating the second switching component.

[0113] Aspect 24: The device according to any one of aspects 22 to 23, wherein the first switching assembly, the second switching assembly, or both comprise a p-mos transistor.

[0114] Aspect 25: The device according to any one of aspects 18 to 24, wherein the controller is further configured such that the device: determines the logic state of the memory cell based at least in part on the transfer of the fourth charge, wherein the logic state of the memory cell is based at least in part on the second voltage of the first node.

[0115] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0116] The terms "electrically connected," "conductively contacted," "connected," and "coupled" refer to the relationship between components that enables the flow of signals between them. Components are considered electrically connected (or conductively contacted, connected, or coupled) to each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between electrically connected (or conductively contacted, connected, or coupled) components may be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the flow of signals between connected components for a period of time.

[0117] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via a conductive path; in a closed-circuit relationship, signals can be transmitted between components via a conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0118] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0119] As used herein, the term “substantially” means that the modified feature (e.g., a verb or adjective modified by the term “substantially”) does not have to be absolute but is close enough to achieve the advantage of the feature.

[0120] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0121] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0122] The exemplary configurations described herein, in conjunction with the accompanying drawings, are not representative of all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and is not "preferred" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0123] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral.

[0124] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including being distributed such that different parts of the functions are implemented in different physical locations.

[0125] For example, the various illustrative blocks and modules described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0126] As used herein, the word "or" in a list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates a comprehensive list, such that a list of at least one of, for example, A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0127] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0128] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will become apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for performing a sensing operation, comprising: During the first phase of a memory cell access operation, a first node and a second node are precharged to a first voltage, the first node being coupled to the second node via a transistor; During the second phase of the access operation, a storage element of the memory cell is coupled to the first node, wherein the storage element is configured to transfer a first charge from the first node based at least in part on the coupling of the storage element to the first node during the second phase of the access operation; During the third phase of the access operation, a second charge is transferred to the second node, wherein the transistor transfers a third charge to the first node based at least in part on the transfer of the second charge to the second node; and During the fourth phase of the access operation, a fourth charge is transferred from the second node, wherein the second voltage of the first node is based at least in part on a fifth charge transferred from the first node during at least one of the third or fourth phases, which is coupled to the storage element and the first node.

2. The method according to claim 1, further comprising: A third voltage is applied to the gate of the transistor, such that the transistor transmits a fourth voltage, not higher than the first voltage, from the second node to the first node during the third phase.

3. The method according to claim 2, wherein the magnitude of the third voltage is greater than the magnitude of the first voltage.

4. The method of claim 2, wherein the transistor transfers at least a portion of the fourth charge from the first node to the second node during the fourth phase based at least in part on applying the third voltage to the gate of the transistor.

5. The method of claim 1, further comprising: During the third phase of the access operation, a pulse is applied to a third node coupled to the second node via a capacitor, wherein the transfer of the second charge to the second node is based at least in part on the application of the pulse.

6. The method of claim 1, wherein the first terminal of the transistor is coupled to the second node, and the second terminal of the transistor is coupled to the first node.

7. The method of claim 1, further comprising: Activate a first switching component coupled to the first node, wherein precharging the first node to the first voltage is based at least in part on activating the first switching component; and Activate a second switching component coupled to the second node, wherein precharging the second node to the first voltage is based at least in part on activating the second switching component.

8. The method of claim 7, further comprising: Deactivate the first switch component; and Deactivate the second switch component, wherein coupling the storage element to the first node is based at least in part on deactivating the first switch component and deactivating the second switch component.

9. The method of claim 7, wherein the first switching component, the second switching component, or both comprise a p-mos transistor.

10. The method of claim 1, further comprising: The logic state of the memory cell is determined at least in part based on the transfer of the fourth charge, wherein the logic state of the memory cell is at least in part based on the second voltage of the first node.

11. The method of claim 1, wherein the second stage and the third stage overlap at least partially in time.

12. The method of claim 1, wherein the magnitude of the first charge is at least partially based on the logic state of the memory cell.

13. The method of claim 1, wherein the memory cell comprises a ferroelectric capacitor.

14. A memory device comprising: A first switching assembly coupled to a first node and configured to precharge the first node to a first voltage during a first phase of an access operation; A transistor having a first terminal coupled to the first node and a second terminal coupled to the second node; A second switching component, coupled to the second node and configured to precharge the second node to the first voltage during the first phase of the access operation; A memory cell includes a storage element and a selection component, the selection component being configured to couple a first node to the storage element during a second phase of the access operation, wherein the storage element is configured to transfer a first charge from the first node based at least in part on coupling the storage element to the first node during the second phase of the access operation; A capacitor, coupled between the second node and the third node; and A pulse generator coupled to the third node and configured to apply a pulse to the third node during a third phase of the access operation, wherein the capacitor is configured to transfer a second charge to the second node at a first transition of the pulse at the third node and transfer a third charge from the second node at a second transition of the pulse at the third node, and wherein the second voltage of the first node is based at least in part on a fourth charge transferred from the first node during the third phase based at least in part on the storage element.

15. The memory device of claim 14, wherein during the third phase of the access operation, the gate voltage of the transistor is biased to a third voltage greater than the first voltage.

16. The memory device of claim 14, wherein the first switching component and the second switching component are activated at least in part based on an activation signal during the first phase, and the coupling of the first node to the memory element is based at least in part on deactivating the first switching component and deactivating the second switching component.

17. The memory device of claim 14, further comprising: A sensing circuit configured to determine the logic state of the memory cell based at least in part on the second voltage of the first node.

18. A memory device comprising: A memory unit, which includes storage elements; and A controller, coupled to the memory cell and configured such that the memory device: During the first phase of the access operation of the memory cell, the first node and the second node are precharged to a first voltage, the first node being coupled to the second node via a transistor; During the second phase of the access operation, the storage element of the memory cell is coupled to the first node, wherein the storage element is configured to transfer a first charge from the first node at least in part based on the coupling of the storage element to the first node during the second phase of the access operation; During the third phase of the access operation, a second charge is transferred to the second node, wherein the transistor is configured to transfer a third charge to the first node based at least in part on the transfer of the second charge to the second node; and During the fourth phase of the access operation, a fourth charge is transferred from the second node, wherein the second voltage of the first node is based at least in part on a fifth charge transferred from the first node during at least one of the third or fourth phases, which is coupled to the storage element and the first node.

19. The memory device of claim 18, wherein the controller is further configured such that the memory device: A third voltage is applied to the gate of the transistor, such that the transistor transmits a fourth voltage, not higher than the first voltage, from the second node to the first node during the third phase.

20. The memory device of claim 19, wherein the magnitude of the third voltage is greater than the magnitude of the first voltage.

21. The memory device of claim 18, wherein a first terminal of the transistor is coupled to the second node, and a second terminal of the transistor is coupled to the first node.

22. The memory device of claim 18, wherein the controller is further configured such that the memory device: Activating a first switching component coupled to the first node, wherein pre-charging the first node to the first voltage is based at least in part on activating the first switching component; and Activate a second switching component coupled to the second node, wherein precharging the second node to the first voltage is based at least in part on activating the second switching component.

23. The memory device of claim 22, wherein the controller is further configured such that the memory device: Deactivate the first switch component; and Deactivate the second switch component, wherein coupling the storage element to the first node is based at least in part on deactivating the first switch component and deactivating the second switch component.

24. The memory device of claim 22, wherein the first switching component, the second switching component, or both comprise a p-mos transistor.

25. The memory device of claim 18, wherein the controller is further configured such that the memory device: The logic state of the memory cell is determined at least in part based on the transfer of the fourth charge, wherein the logic state of the memory cell is at least in part based on the second voltage of the first node.

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