11 results about "Presynaptic neuron" patented technology

The invention discloses a synaptic plastic mechanism bionic circuit based on a threshold symmetric memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a pre-synaptic neuron circuit, the threshold symmetric memristor and a post-synaptic neuron circuit; the bionic circuit is divided into an excitatory synaptic moldability mechanism circuit and an inhibitory synaptic moldability mechanism circuit according to a synaptic moldability mechanism; the design method of the circuit comprises the following steps: firstly, designing neuron waveforms before and after synapse, then traversing changes of memristive synapse conductance values at different time intervals to obtain a corresponding curve of the conductance changes and the time intervals, verifying the fitting degree of a biological synapse plastic mechanism curve and the curve, and if the fitting degree is low, determining that the biological synapse plastic mechanism curve is not matched with the curve. And if not, redesigning the pulse waveforms before and after synapse. The synaptic plasticity mechanism simulated by the bionic circuit provided by the invention and a biological synaptic STDP mechanism model have a small fitting error, the provided design method is higher in universality, circuit parameters can be adjusted according to different memristors, and different forms of biological synaptic plasticity mechanisms can be simulated.

The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit comprises at least: a first transistor, a weight unit, a second transistor, a third transistor, and a fourth transistor; the present application also relates to an electronic device comprising the aforementioned neural network circuit.

This invention relates to the field of neuromorphic computing technology and provides a method and system for dynamic adjustment of synaptic weights in real-time neurofeedback for neuromorphic chips. The method includes: capturing the pulse signals and timestamps emitted by presynaptic and postsynaptic neurons; calculating the time difference between the presynaptic and postsynaptic pulses; when the absolute value of the time difference is less than a preset time window threshold, querying a pulse timing dependency plasticity rule base based on the sign of the time difference to determine the corresponding synaptic weight adjustment type; generating corresponding voltage pulse parameters based on the adjustment type and the current conductance state of the target memristor synapse; and applying a write voltage pulse to the target memristor synapse according to the voltage pulse parameters to adjust its conductance value in situ in real time, thereby dynamically updating the synaptic weights. This invention solves the problems of poor dynamic environment adaptability, low energy efficiency, and high learning latency caused by traditional offline weight update mechanisms.

The application provides a brain-like synapse learning method and a brain-like technology neural morphological hardware system, and the method comprises the following steps: determining a pulse pair generated by a presynaptic neuron and a postsynaptic neuron in a brain-like synapse learning circuit, wherein the pulse pair comprises an input pulse generated by the presynaptic neuron and an output pulse generated by the postsynaptic neuron; determining an STDP mechanism corresponding to the pulse pair and a synapse weight corresponding to the STDP mechanism based on the pulse pair; and performing STDP learning corresponding to the brain-like synapse learning circuit based on the pulse pair and the synapse weight; wherein the STDP mechanism is a pulse time-dependent plasticity mechanism, and the front and rear pulses of the pulse pair correspond to a long-term potentiation process or a long-term depression process in the STDP mechanism according to the time sequence. The application realizes online learning of brain-like intelligence, and plays the environment self-adaptive characteristics of brain-like computing.

The application discloses a hybrid integrated photon pulse neural network device, comprising: an optical coding module comprising N presynaptic neurons; an optical response output module comprising N postsynaptic neurons; the neurons are VCSEL-SAs, and N is greater than or equal to 1; an optical synapse module comprising a first MZI subnetwork, an MZI array and a second MZI subnetwork in sequence, forming an MZI network with N inputs and N outputs; the first MZI subnetwork and the second MZI subnetwork each comprise N(N-1) / 2 MZIs arranged in a Reck architecture, and the MZI array comprises N MZIs arranged in parallel; the phase parameters of the MZIs in the optical synapse module are obtained by singular value decomposition of an N*N weight matrix, construction of an equation group containing trigonometric functions based on a unitary matrix obtained by decomposition and solution of the equation group.

The invention relates to the technical field of neuron circuits, and provides a configurable neuron circuit and a control method, and the circuit comprises a mode selection module which selects a corresponding target working mode according to a received neuron configuration signal; the calculation module is connected to the mode selection module, and performs corresponding membrane potential updating according to the target working mode selected by the mode selection module and the received pulse information of the presynaptic neurons to obtain a membrane potential updating result; the comparison module is connected to the calculation module and is used for comparing the membrane potential updating result with a preset threshold value and determining whether the current neuron can generate a pulse or not according to a comparison result; and the pulse generation module is connected to the comparison module, and is used for generating a pulse signal and an AER (Advanced Encryption Register) coding group package and outputting updated membrane potential information when the current neuron is determined to generate the pulse. According to the technical scheme, selection of two neuron models can be achieved, the circuit structure is simplified, and meanwhile more complex behavior modes are achieved.

A method (100) for distributed learning of a temporal neural network in a communication network. The method is performed by a first node of the communication network, the first node associated to a pre-synaptic neuron of the temporal neural network. The method comprises receiving (S101), from a second node of the communication system, the second node associated to a post-synaptic neuron of the temporal neural network, an indication that a hidden state of the post- synaptic neuron has changed. The method comprises transmitting (S102), to the second node, a pre-synaptic stimuli and receiving (S103), with a scheduled acknowledgement message associated to the transmitted pre-synaptic stimuli, a hidden state information related to the post-synaptic neuron. Further disclosed are related apparatuses, computer programs, and computer program products.

A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

The invention discloses a memristor neural network circuit based on emotion influence STDP learning rate, which realizes biological synaptic plasticity through resistance plasticity and threshold value characteristics of a memristor, and simulates the regulation effect of emotion on brain learning rate. The circuit is composed of a pre-synaptic neuron, a post-synaptic neuron, a pulse module and a sensitive module. Wherein the pre-synaptic neurons and the post-synaptic neurons receive environment input signals and emotion signals, and the input mood signals are learned by using the weight adjustment module and the memristor; the pulse module compares a difference value between the neuron output signal and the emotion signal, and outputs a pulse signal when the difference value is lower than a threshold voltage; the sensitive module dynamically adjusts the resistance value of the memristor according to the pulse signal so as to simulate the emotion, thereby adjusting the weight and adjusting the voltage. When the emotion is excited, the learning rate is increased; when the emotion is low, the learning rate is reduced, and the circuit effectively simulates the influence of the emotion on the STDP learning rate.

A neuromorphic circuit (500) includes a crossbar synapse array unit. The crossbar synapse array unit includes a complementary metal oxide semiconductor (CMOS) transistor (T6), the on-resistance of which is controlled by the gate voltage of the CMOS transistor (T6) to update the weight of the crossbar synapse array unit. The neuromorphic circuit (500) also includes a set of row lines, each of which connects the synapse array unit in series with a plurality of presynaptic neurons at a first end of the synapse array unit. The neuromorphic circuit (500) also includes a set of column lines, each of which connects the synapse array unit in series with a plurality of postsynaptic neurons at a second end of the synapse array unit. The gate voltage of the CMOS transistor (T6) is controlled by performing a charge sharing technique, wherein the charge sharing technique uses non-overlapping pulses on a cell control line aligned with the set of row lines and the set of column lines to update the weight of the crossbar synapse array unit.

The invention relates to the technical field of neural networks, and discloses a spiking neural network acceleration method and device, equipment, a storage medium and a product, and the method comprises the steps: carrying out the descending sorting of pre-synaptic neurons according to the weight; gradually accumulating the weights of the activated pre-synaptic neurons into the membrane potential of the post-synaptic neurons according to the sorting sequence; in the step-by-step accumulation process, when the membrane potential of the post-synaptic neurons is larger than the excitation threshold potential, the post-synaptic neurons output pulses so as to improve the calculation efficiency.