Digital clock duty ratio calibrating circuit

Abstract

The invention relates to a digital clock dutyfactor calibration circuit, which is mainly used for calculating the dutyfactor of a system clock in a high-speed data communication system and a DSP system (such as a high-speed data storage device, a pipelining processor, etc.). In the circuit, an input terminal of an input buffer (10) is connected with an original input clock signal (CKI) to be calculated; the output terminal signal of the input buffer (10) that is an input clock signal after being buffered (CKB), the output terminal signal of a half cycle delay line HCDL (20) that is a half cycle delay clock signal (CKD) and the output terminal signal of a matching delay-line (30) that is a matching delay clock signal (CKM) are respectively connected with a reset input terminal R and a set input terminal S of an RS trigger (40); the signal at an output terminal Q of the RS trigger (40) is a calibration clock signal (CKO) with dutyfactor of 50 percent after being calculated; and the input buffer (10) plays the role of ensuring the fan-out ability of the clock signal on a subsequent circuit.

Description

technical field [0001] The invention is mainly used in high-speed data communication systems and digital signal processing systems (such as high-speed data storage, pipeline processors, etc.) to correct the duty cycle of the system clock, and belongs to the technical field of duty cycle calibration circuit design. Background technique [0002] With the advancement of integrated circuit technology, the main frequency of modern digital systems has been continuously increased, and technologies such as double data rate (DDR) and pipelines have been widely used to obtain greater data throughput. Therefore, the digital system also puts forward higher requirements on the signal quality of the working clock. A high-quality clock signal should have the characteristics of fast establishment, low jitter, and low skew, and a 50% duty cycle to ensure that the relevant timing constraints of data signal establishment and retention during transmission are met, and the system can be stable. ...

AI Technical Summary

Problems solved by technology

Generally speaking, the analog method can obtain higher duty cycle correction accuracy, work at a higher frequency, and obtain smaller edge jitter, but the analog method also has long settling time, difficulty in system stability design, and process constraints. - Disadvantages of obvious influence of voltage-temperature (P.V.T.) variation

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