84 results about "Current conveyor" patented technology

A sensor array includes a plurality of pixel sensor circuits; and a current-mode readout circuit to sample signals generated in each pixel sensor circuit; and addressing circuitry to individually select each pixel sensor circuit. Each pixel sensor circuit includes: a transducer and an amplifying element coupled to the transducer and configured to output a signal current which varies as a function of a measured physical property. The current-mode readout circuit includes: a sense signal line coupled to each of the amplifying elements in order to monitor the voltage presented across the amplifying element of the selected pixel sensor circuit; a drive signal line coupled to an output of each of the amplifying elements in order to provide a constant bias voltage to the amplifying element of the selected pixel sensor circuit; and a current conveyor circuit coupled to the sense signal line and drive signal line.

A large-scale field-programmable analog array (FPAA) for rapidly prototyping analog systems and an arbitrary analog waveform generator. The large-scale FPAA includes a floating-gate transistor array and a plurality of computational analog blocks (CABs), which may be adapted to set bias voltages for operational transconductance amplifiers (OTAs), adjust corner frequencies on the capacitively coupled current conveyors, set multiplier coefficients in vector-matrix multipliers, and a variety of other operations. The floating-gate transistors may be used as switch elements, programmable resistor elements, precision current sources, and programmable transistors. Accordingly, the floating-gate transistors within the array allow on-chip programming of the characteristics of the computational elements, while still maintaining compact CABs. The arbitrary analog waveform generator may include programmable floating-gate MOS transistors for use as analog memory cells to store samples of the waveforms.

The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.

A shunt type voltage regulator circuit (300) can include a load supply circuit (306) and feedback circuit (308-0) that provide impedance modulated according to a first feedback circuit (308), thus limiting power consumption at higher power supply ranges. In addition, a faster regulation response can be provided by a current conveyor circuit (312′) that can force the voltage at a regulated load node (304) to match that at a replication node (316).

The invention discloses a floating memory capacitor and memory inductor simulator based on a memory resistor. The floating memory capacitor and memory inductor simulator based on the memory resistor comprises a first differential difference current conveyor, a second differential difference current conveyor, the memory resistor, a resistor and a reactance element, wherein the X end of the first differential difference current conveyor is connected with the ground after being connected with the memory resistor, one input end of the second differential difference current conveyor is connected with the ground, the other input end of the second differential difference current conveyor is connected with the in-phase current output end of the first differential difference current conveyor and one end of the reactance element, the other end of the reactance element is connected with the ground, the X end of the second differential difference current conveyor is connected with the ground after being connected with the resistor, the in-phase current output end and the reverse current output end of the second differential difference current conveyor are connected with two input ends of the first differential difference current conveyor respectively. The floating memory capacitor and memory inductor simulator based on the memory resistor has the advantages that the simulator can effectively replace an actual memory capacitor and memory inductor to design a circuit, voltage at the two ends of the memory capacitor and voltage at the two ends of the memory inductor are not limited, and the simulator can be connected with other electronic elements flexibly.

A replica biased voltage regulator circuit (100) is disclosed that provides high frequency response via local positive feedback and low frequency response via a negative feedback loop. A voltage regulator circuit (100) can include current conveyor (106) that essentially forces an output voltage (Vload) to follow a replica voltage (Vrep). An operational amplifier (102) can provide negative feedback by controlling current supplied to the current conveyor (104) based on a comparison between a reference voltage (Vref) and the replica voltage (Vrep).

A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected.

The invention provides a process deviation tolerating and reading interference eliminating reading amplifying circuit, which consists of a current conveyor, a load circuit, a charge transferring voltage amplifier and a dynamic latch voltage comparator, wherein one input end Y of the current conveyor is connected with an STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) data unit array to be read and an STT-MRAM reference unit array to be read through a bit line selector; the other input end X of the current conveyor is connected with an external bias voltage V<bias>; the output end Z of the current conveyor is simultaneously connected with the load circuit and the input end of the charge transferring voltage amplifier; the other end of the load circuit is connected with a power supply voltage source Vdd; the output end of the charge transferring voltage amplifier is connected with the input end of the dynamic latch voltage comparator; and the output end of the dynamic latch voltage comparator outputs final read binary data signals. The reading amplifying circuit provided by the invention has the advantages that the problem of conflict between the reading interference and the reading judging allowance in the STT-MRAM technology is solved, and the reading reliability of an STT-MRAM is improved.

The invention discloses a replica biased voltage regulator circuit (100) that provides high frequency response via local positive feedback and low frequency response via a negative feedback loop. A voltage regulator circuit (100) can include current conveyor (106) that essentially forces an output voltage (Vload) to follow a replica voltage (Vrep). An operational amplifier (102) can provide negative feedback by controlling current supplied to the current conveyor (104) based on a comparison between a reference voltage (Vref) and the replica voltage (Vrep).

A circuit having a first transistor being a common gate connected transistor and a second transistor, the second transistor being M times the size of the first transistor, the first and second transistors having commonly connected gates and commonly connected drains, wherein an apparatus is provided to regulate the source voltage of the second transistor to track the source voltage of the first transistor, wherein the current gain of the circuit is M+1.

The invention provides an intelligent sorting system of caterpillar fungus and a utilization method of the intelligent sorting system. The intelligent sorting system comprises a conveyor belt, a motor, a sliding shoe, a camera lens, a microprocessor, an LCD (Liquid Crystal Display), an upper computer camera lens and an upper computer, wherein the conveyor belt is used for conveying the caterpillarfungus needing to be sorted; the motor is used for controlling the conveyor belt to operate; the sliding shoe is used for sorting the caterpillar fungus of a corresponding path opening; the camera lens is located above the sorting path opening and is used for acquiring a caterpillar fungus image; the microprocessor is connected with a camera through a serial port and is used for transplanting OpenCV to carry out image processing; a caterpillar fungus type is identified through a convolutional neural network based on a SUPF algorithm; graded sorting is carried out through Canny edge detectionand a Hu matrix algorithm and the sliding shoe is controlled to carry out sorting; the LCD is used for displaying acquired caterpillar fungus information; the upper computer camera lens is used for monitoring a sorting condition and feeding the sorting condition back to the upper computer in real time; the upper computer is used for displaying a current sorting condition in real time and acquiringthe quantity of the caterpillar fungus on the current conveyor belt through image processing, so as to control the speed of the motor. The intelligent sorting system provided by the invention can beused for identifying and positioning the caterpillar fungus with different species and different grades and the sorting error rate is reduced.

A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint sub-circuitry, A new ASM can effectively carry out (i) use of all the grounded capacitors and grounded resistors, and (ii) employment of the minimum number of active and passive components and then enjoys the low sensitivities, lower parasitics, power consumption, noise, and smaller chip area leading to simultaneously achieving two important features: (i) higher output performance and (ii) lower cost, without tradeoff. Moreover, the component value variations of all the relative sensitivities have the same incremental percentage or decrement.

In one embodiment, a programmable gain instrumentation amplifier (PGIA) comprises a pair of current conveyors, each current conveyor having a respective sense node and a respective voltage input, with a gain-setting resistor coupled between the respective sense nodes, and current being sensed on both sides of the gain setting resistor. In one embodiment, each current conveyor comprises a corresponding operational amplifier (op-amp) having a non-inverting input configured as the respective voltage input that may receive a respective input voltage signal, an output and an inverting input, with a respective current conveying element, which may be a FET, configured in a feedback loop between the output and the inverting input. Each current conveyor may be configured to sense a corresponding current flowing through its respective FET, with the corresponding currents forming a differential output current of the PGIA. The respective input voltage signals received by the respective voltage inputs may form a differential input voltage of the PGIA. In one set of embodiments, the PGIA may be implemented with a differential voltage output, leading to an increased output swing for higher signal-to-noise ratio and increased symmetry for a higher common mode rejection ratio.

The present invention relates to a current conveyor circuit capable of operating at very low voltages, said circuit comprising: three LVCM's and four MOSFETS, wherein LVCM1 provides a constant bias current to flow through M3, if port X is kept open and the difference between the bias current and the injected current flows through M3 if a current is injected into port X, which gets reflected at port Z due to the action of LVCM1, M3 and M4, LVCM2 maintains the drain currents of M1 and M2 constant, and LVCM3 maintains a constant tail current in the circuit.

A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.