Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit

Abstract

The invention relates to a control method for a low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit. The low-power STT-RAM reading circuit is provided and comprises a control circuit, a parallel magnetic tunnel junction, an open-loop amplifier, a control logic circuit, a first phase inverter, a first D trigger, a second D trigger and a clock output module; the low-power STT-RAM reading circuit is controlled to enter a working or standby state through the control circuit, so that data stored in the parallel magnetic tunnel junction is read. A tree-type reading scheme is adopted, so that the reading speed is relatively high; the control circuit is introduced and the power consumption is generated only when the reading circuit enters the working state, so that the power consumption of the reading circuit is reduced.

Description

technical field

[0001] The invention relates to a control method of a low power consumption two-stage amplifier STT-RAM reading circuit. Background technique

[0002] Traditional Random Access Memory (RAM) such as Dynamic Random Access Memory (DRAM) is relatively inexpensive, but has slower access speeds, poor durability and data can only be stored for a short period of time. Since the data must be refreshed once in a while, this in turn leads to higher power consumption. Static random access memory (SRAM) has the advantages of fast access speed, low power consumption, and non-volatility, but it is expensive and has low integration.

[0003] In recent years, the emerging spin transfer torque random access memory (STT-RAM) is expected to become the first choice for future caches due to its high density, low leakage current, non-volatility, ultra-long durability, and fast read and write. product.

[0004] This patent is based on a novel tree-type reading circuit scheme, and...

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