Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit

A technology of STT-RAM and reading circuit, which is applied in the control field of low-power two-stage amplifier STT-RAM reading circuit, which can solve the problems of increasing the total power consumption of the reading circuit, so as to save restart time and reduce the difficulty of use , the effect of improving the reading speed

Active Publication Date: 2015-07-22
FUZHOU UNIVERSITY
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, the use of a two-stage operational amplifier cascaded structure alone will generate additional static power consumption when it is not working, which greatly increases the total power consumption of the entire reading circuit, so in order to con

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  • Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit
  • Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit
  • Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit

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Embodiment Construction

[0032] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0033] Such as Figure 1-7 As shown, a control method of a low-power two-stage amplifier STT-RAM read circuit of the present invention comprises the following steps,

[0034] Step S1: providing a low-power consumption STT-RAM reading circuit, including a control circuit, a parallel magnetic tunnel junction, an open-loop amplifier, a control logic circuit, a first inverter, a first D flip-flop, a second D flip-flop, Clock output module; the control circuit, the parallel magnetic tunnel junction, and the open-loop amplifier are connected to each other, and the open-loop amplifier is also connected to the control logic circuit and the first inverter, and the first inverter is connected to the first inverter. The first D flip-flop is connected to the second D flip-flop, the first clock signal output end and the second clock signal output end...

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Abstract

The invention relates to a control method for a low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit. The low-power STT-RAM reading circuit is provided and comprises a control circuit, a parallel magnetic tunnel junction, an open-loop amplifier, a control logic circuit, a first phase inverter, a first D trigger, a second D trigger and a clock output module; the low-power STT-RAM reading circuit is controlled to enter a working or standby state through the control circuit, so that data stored in the parallel magnetic tunnel junction is read. A tree-type reading scheme is adopted, so that the reading speed is relatively high; the control circuit is introduced and the power consumption is generated only when the reading circuit enters the working state, so that the power consumption of the reading circuit is reduced.

Description

technical field [0001] The invention relates to a control method of a low power consumption two-stage amplifier STT-RAM reading circuit. Background technique [0002] Traditional Random Access Memory (RAM) such as Dynamic Random Access Memory (DRAM) is relatively inexpensive, but has slower access speeds, poor durability and data can only be stored for a short period of time. Since the data must be refreshed once in a while, this in turn leads to higher power consumption. Static random access memory (SRAM) has the advantages of fast access speed, low power consumption, and non-volatility, but it is expensive and has low integration. [0003] In recent years, the emerging spin transfer torque random access memory (STT-RAM) is expected to become the first choice for future caches due to its high density, low leakage current, non-volatility, ultra-long durability, and fast read and write. product. [0004] This patent is based on a novel tree-type reading circuit scheme, and...

Claims

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Application Information

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IPC IPC(8): G11C7/06
Inventor 魏榕山王珏郭仕忠于静胡惠文张泽鹏何明华
Owner FUZHOU UNIVERSITY
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