This invention discloses a unified intermediate representation
data model and construction method for hardware design, belonging to the field of
electronic design automation. The model includes: a unified representation
base class; structural relationship graph representation and temporal behavior representation, describing the
structural composition and runtime behavior of the design, respectively; formal
semantic consistency constraints to ensure
semantic consistency between structure and behavior; and a
semantic association architecture to establish bidirectional
semantic mapping between various
scenario representations such as HDL code, schematics, and waveforms and the unified representation
base class. The construction method based on this model includes an incremental synchronization process, achieving automatic synchronization after any representation modification through change capture, cross-representation mapping indexing, and
change propagation rules. This invention also provides an AI-assisted design method based on this model, improving AI interaction efficiency and the
automation level of design
verification through multi-dimensional context construction,
syntax stripping, incremental interaction protocols, and automatic closed-loop
verification.